Holger Brunck | ddef889 | 2020-02-19 19:55:14 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: BSD-3-Clause */ |
| 2 | /* |
| 3 | * Altera SoCFPGA SDRAM configuration |
| 4 | * |
| 5 | */ |
| 6 | |
| 7 | #ifndef __SOCFPGA_SDRAM_CONFIG_H__ |
| 8 | #define __SOCFPGA_SDRAM_CONFIG_H__ |
| 9 | |
| 10 | /* SDRAM configuration */ |
Tom Rini | dcdd3bd | 2022-10-28 20:27:14 -0400 | [diff] [blame^] | 11 | #define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A |
| 12 | #define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 |
| 13 | #define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 |
| 14 | #define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 |
| 15 | #define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 |
| 16 | #define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 |
| 17 | #define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 |
| 18 | #define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 |
| 19 | #define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 |
| 20 | #define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 1 |
| 21 | #define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 |
| 22 | #define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 |
| 23 | #define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 |
| 24 | #define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 |
| 25 | #define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 |
| 26 | #define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 |
| 27 | #define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 |
| 28 | #define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 14 |
| 29 | #define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 |
| 30 | #define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 |
| 31 | #define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 |
| 32 | #define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 |
| 33 | #define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 |
| 34 | #define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 |
| 35 | #define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 5 |
| 36 | #define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 4 |
| 37 | #define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16 |
| 38 | #define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 60 |
| 39 | #define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4 |
| 40 | #define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 5 |
| 41 | #define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 2341 |
| 42 | #define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 5 |
| 43 | #define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 5 |
| 44 | #define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 2 |
| 45 | #define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 |
| 46 | #define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 2 |
| 47 | #define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 13 |
| 48 | #define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 17 |
| 49 | #define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 |
| 50 | #define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 |
| 51 | #define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 200 |
| 52 | #define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 3 |
| 53 | #define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 3 |
| 54 | #define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 3 |
| 55 | #define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 |
| 56 | #define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 |
| 57 | #define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 |
| 58 | #define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 |
| 59 | #define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 |
| 60 | #define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 |
| 61 | #define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 |
| 62 | #define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 |
| 63 | #define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 |
| 64 | #define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 |
| 65 | #define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 |
| 66 | #define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0 |
| 67 | #define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 |
| 68 | #define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 |
| 69 | #define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 |
| 70 | #define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 |
| 71 | #define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441 |
| 72 | #define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78 |
| 73 | #define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 |
| 74 | #define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0 |
| 75 | #define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 |
| 76 | #define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 |
| 77 | #define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 |
| 78 | #define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 |
| 79 | #define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 |
| 80 | #define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 |
Holger Brunck | ddef889 | 2020-02-19 19:55:14 +0100 | [diff] [blame] | 81 | |
| 82 | /* Sequencer auto configuration */ |
| 83 | #define RW_MGR_ACTIVATE_0_AND_1 0x11 |
| 84 | #define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x12 |
| 85 | #define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x14 |
| 86 | #define RW_MGR_CLEAR_DQS_ENABLE 0x4B |
| 87 | #define RW_MGR_EMR 0x09 |
| 88 | #define RW_MGR_EMR2 0x0D |
| 89 | #define RW_MGR_EMR3 0x0F |
| 90 | #define RW_MGR_EMR_OCD_ENABLE 0x0B |
| 91 | #define RW_MGR_GUARANTEED_READ 0x4E |
| 92 | #define RW_MGR_GUARANTEED_READ_CONT 0x56 |
| 93 | #define RW_MGR_GUARANTEED_WRITE 0x1A |
| 94 | #define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1D |
| 95 | #define RW_MGR_GUARANTEED_WRITE_WAIT1 0x21 |
| 96 | #define RW_MGR_GUARANTEED_WRITE_WAIT2 0x1B |
| 97 | #define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1F |
| 98 | #define RW_MGR_IDLE 0x00 |
| 99 | #define RW_MGR_IDLE_LOOP1 0x77 |
| 100 | #define RW_MGR_IDLE_LOOP2 0x76 |
| 101 | #define RW_MGR_INIT_CKE_0 0x71 |
| 102 | #define RW_MGR_LFSR_WR_RD_BANK_0 0x24 |
| 103 | #define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x27 |
| 104 | #define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x26 |
| 105 | #define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x25 |
| 106 | #define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x34 |
| 107 | #define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x23 |
| 108 | #define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x38 |
| 109 | #define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x3B |
| 110 | #define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x3A |
| 111 | #define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x39 |
| 112 | #define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x48 |
| 113 | #define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x37 |
| 114 | #define RW_MGR_MR_CALIB 0x05 |
| 115 | #define RW_MGR_MR_DLL_RESET 0x07 |
| 116 | #define RW_MGR_MR_USER 0x03 |
| 117 | #define RW_MGR_NOP 0x01 |
| 118 | #define RW_MGR_PRECHARGE_ALL 0x16 |
| 119 | #define RW_MGR_READ_B2B 0x5B |
| 120 | #define RW_MGR_READ_B2B_WAIT1 0x63 |
| 121 | #define RW_MGR_READ_B2B_WAIT2 0x6D |
| 122 | #define RW_MGR_REFRESH 0x18 |
| 123 | |
| 124 | /* Sequencer defines configuration */ |
| 125 | #define AFI_CLK_FREQ 301 |
| 126 | #define AFI_RATE_RATIO 1 |
| 127 | #define CALIB_LFIFO_OFFSET 6 |
| 128 | #define CALIB_VFIFO_OFFSET 4 |
| 129 | #define ENABLE_SUPER_QUICK_CALIBRATION 0 |
| 130 | #define IO_DELAY_PER_DCHAIN_TAP 25 |
| 131 | #define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 |
| 132 | #define IO_DELAY_PER_OPA_TAP 416 |
| 133 | #define IO_DLL_CHAIN_LENGTH 8 |
| 134 | #define IO_DQDQS_OUT_PHASE_MAX 0 |
| 135 | #define IO_DQS_EN_DELAY_MAX 31 |
| 136 | #define IO_DQS_EN_DELAY_OFFSET 0 |
| 137 | #define IO_DQS_EN_PHASE_MAX 7 |
| 138 | #define IO_DQS_IN_DELAY_MAX 31 |
| 139 | #define IO_DQS_IN_RESERVE 4 |
| 140 | #define IO_DQS_OUT_RESERVE 4 |
| 141 | #define IO_IO_IN_DELAY_MAX 31 |
| 142 | #define IO_IO_OUT1_DELAY_MAX 31 |
| 143 | #define IO_IO_OUT2_DELAY_MAX 0 |
| 144 | #define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 |
| 145 | #define MAX_LATENCY_COUNT_WIDTH 5 |
| 146 | #define READ_VALID_FIFO_SIZE 16 |
| 147 | #define REG_FILE_INIT_SEQ_SIGNATURE 0x555504bf |
| 148 | #define RW_MGR_MEM_ADDRESS_MIRRORING 0 |
| 149 | #define RW_MGR_MEM_DATA_MASK_WIDTH 4 |
| 150 | #define RW_MGR_MEM_DATA_WIDTH 32 |
| 151 | #define RW_MGR_MEM_DQ_PER_READ_DQS 8 |
| 152 | #define RW_MGR_MEM_DQ_PER_WRITE_DQS 8 |
| 153 | #define RW_MGR_MEM_IF_READ_DQS_WIDTH 4 |
| 154 | #define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4 |
| 155 | #define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1 |
| 156 | #define RW_MGR_MEM_NUMBER_OF_RANKS 1 |
| 157 | #define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1 |
| 158 | #define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1 |
| 159 | #define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4 |
| 160 | #define TINIT_CNTR0_VAL 74 |
| 161 | #define TINIT_CNTR1_VAL 20 |
| 162 | #define TINIT_CNTR2_VAL 20 |
| 163 | #define TRESET_CNTR0_VAL 74 |
| 164 | #define TRESET_CNTR1_VAL 99 |
| 165 | #define TRESET_CNTR2_VAL 10 |
| 166 | |
| 167 | /* Sequencer ac_rom_init configuration */ |
| 168 | const u32 ac_rom_init[] = { |
| 169 | 0x30700000, |
| 170 | 0x38700000, |
| 171 | 0x30700000, |
| 172 | 0x20700000, |
| 173 | 0x10000853, |
| 174 | 0x10000853, |
| 175 | 0x10000953, |
| 176 | 0x10010000, |
| 177 | 0x10010380, |
| 178 | 0x10020000, |
| 179 | 0x10030000, |
| 180 | 0x10300400, |
| 181 | 0x10600000, |
| 182 | 0x10620000, |
| 183 | 0x10200400, |
| 184 | 0x10400000, |
| 185 | 0x1c900000, |
| 186 | 0x1c920000, |
| 187 | 0x1c900008, |
| 188 | 0x1c920008, |
| 189 | 0x38f00000, |
| 190 | 0x3cf00000, |
| 191 | 0x38700000, |
| 192 | 0x10100000, |
| 193 | 0x18900000, |
| 194 | 0x13500000, |
| 195 | 0x13520000, |
| 196 | 0x13500008, |
| 197 | 0x13520008, |
| 198 | 0x33700000, |
| 199 | 0x10500008 |
| 200 | }; |
| 201 | |
| 202 | /* Sequencer inst_rom_init configuration */ |
| 203 | const u32 inst_rom_init[] = { |
| 204 | 0x80180, |
| 205 | 0x100, |
| 206 | 0x80000, |
| 207 | 0x200, |
| 208 | 0x80000, |
| 209 | 0x280, |
| 210 | 0x80000, |
| 211 | 0x300, |
| 212 | 0x80000, |
| 213 | 0x380, |
| 214 | 0x80000, |
| 215 | 0x400, |
| 216 | 0x80000, |
| 217 | 0x480, |
| 218 | 0x80000, |
| 219 | 0x500, |
| 220 | 0x80000, |
| 221 | 0x600, |
| 222 | 0x8000, |
| 223 | 0x680, |
| 224 | 0xa000, |
| 225 | 0x80000, |
| 226 | 0x700, |
| 227 | 0x80000, |
| 228 | 0x780, |
| 229 | 0x80000, |
| 230 | 0x968, |
| 231 | 0xcae8, |
| 232 | 0x8e8, |
| 233 | 0x8ae8, |
| 234 | 0x988, |
| 235 | 0xea88, |
| 236 | 0x808, |
| 237 | 0xaa88, |
| 238 | 0x80000, |
| 239 | 0xcc00, |
| 240 | 0xcb80, |
| 241 | 0xe080, |
| 242 | 0xa00, |
| 243 | 0x20ae0, |
| 244 | 0x20ae0, |
| 245 | 0x20ae0, |
| 246 | 0x20ae0, |
| 247 | 0xb00, |
| 248 | 0x0, |
| 249 | 0x0, |
| 250 | 0x0, |
| 251 | 0x0, |
| 252 | 0x60c80, |
| 253 | 0x60e80, |
| 254 | 0x60e80, |
| 255 | 0x60e80, |
| 256 | 0xa000, |
| 257 | 0x8000, |
| 258 | 0x80000, |
| 259 | 0xcc00, |
| 260 | 0xcb80, |
| 261 | 0xe080, |
| 262 | 0xa00, |
| 263 | 0x30ae0, |
| 264 | 0x30ae0, |
| 265 | 0x30ae0, |
| 266 | 0x30ae0, |
| 267 | 0xb00, |
| 268 | 0x0, |
| 269 | 0x0, |
| 270 | 0x0, |
| 271 | 0x0, |
| 272 | 0x70c80, |
| 273 | 0x70e80, |
| 274 | 0x70e80, |
| 275 | 0x70e80, |
| 276 | 0xa000, |
| 277 | 0x8000, |
| 278 | 0x80000, |
| 279 | 0xf58, |
| 280 | 0x58, |
| 281 | 0x80000, |
| 282 | 0xf68, |
| 283 | 0x168, |
| 284 | 0x168, |
| 285 | 0x8168, |
| 286 | 0x40de8, |
| 287 | 0x40ee8, |
| 288 | 0x40ee8, |
| 289 | 0x40ee8, |
| 290 | 0xf68, |
| 291 | 0x168, |
| 292 | 0x168, |
| 293 | 0xa168, |
| 294 | 0x80000, |
| 295 | 0x40c88, |
| 296 | 0x40e88, |
| 297 | 0x40e88, |
| 298 | 0x40e88, |
| 299 | 0x40d68, |
| 300 | 0x40ee8, |
| 301 | 0x40ee8, |
| 302 | 0x40ee8, |
| 303 | 0xa000, |
| 304 | 0x40de8, |
| 305 | 0x40ee8, |
| 306 | 0x40ee8, |
| 307 | 0x40ee8, |
| 308 | 0x40e08, |
| 309 | 0x40e88, |
| 310 | 0x40e88, |
| 311 | 0x40e88, |
| 312 | 0xf00, |
| 313 | 0xc000, |
| 314 | 0x8000, |
| 315 | 0xe000, |
| 316 | 0x80000, |
| 317 | 0x180, |
| 318 | 0x8180, |
| 319 | 0xa180, |
| 320 | 0xc180, |
| 321 | 0x80180, |
| 322 | 0x8000, |
| 323 | 0xa000, |
| 324 | 0x80000 |
| 325 | }; |
| 326 | |
| 327 | #endif /* __SOCFPGA_SDRAM_CONFIG_H__ */ |