blob: c89b08d5ea17da59bc3988d20bcb526509be684c [file] [log] [blame]
Simon Glass18d4a112024-10-23 15:20:12 +02001/** @file
2 *
3 * Differentiated System Definition Table (DSDT)
4 *
5 * Copyright (c) 2020, Pete Batard <pete@akeo.ie>
6 * Copyright (c) 2018-2020, Andrey Warkentin <andrey.warkentin@gmail.com>
7 * Copyright (c) Microsoft Corporation. All rights reserved.
8 * Copyright (c) 2021, ARM Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: BSD-2-Clause-Patent
11 *
12 **/
13
14#include <asm/arch/acpi/bcm2711.h>
15#include <asm/arch/acpi/bcm2836.h>
16#include <asm/arch/acpi/bcm2836_gpio.h>
17#include <asm/arch/acpi/bcm2836_gpu.h>
18#include <asm/arch/acpi/bcm2836_pwm.h>
19#include <asm/arch/acpi/bcm2836_sdio.h>
20#include <asm/arch/acpi/bcm2836_sdhost.h>
21
22#include "acpitables.h"
23
24#define BCM_ALT0 0x4
25#define BCM_ALT1 0x5
26#define BCM_ALT2 0x6
27#define BCM_ALT3 0x7
28#define BCM_ALT4 0x3
29#define BCM_ALT5 0x2
30
31//
32// The ASL compiler does not support argument arithmetic in functions
33// like QWordMemory (). So we need to instantiate dummy qword regions
34// that we can then update the Min, Max and Length attributes of.
35// The three macros below help accomplish this.
36//
37// QWORDMEMORYSET specifies a CPU memory range (whose base address is
38// BCM2836_SOC_REGISTERS + Offset), and QWORDBUSMEMORYSET specifies
39// a VPU memory range (whose base address is provided directly).
40//
41#define QWORDMEMORYBUF(Index) \
42 QWordMemory (ResourceProducer,, \
43 MinFixed, MaxFixed, NonCacheable, ReadWrite, \
44 0x0, 0x0, 0x0, 0x0, 0x1,,, RB ## Index)
45
46#define QWORDMEMORYSET(Index, Offset, Length) \
47 CreateQwordField (RBUF, RB ## Index._MIN, MI ## Index) \
48 CreateQwordField (RBUF, RB ## Index._MAX, MA ## Index) \
49 CreateQwordField (RBUF, RB ## Index._LEN, LE ## Index) \
50 Store (Length, LE ## Index) \
51 Add (BCM2836_SOC_REGISTERS, Offset, MI ## Index) \
52 Add (MI ## Index, LE ## Index - 1, MA ## Index)
53
54#define QWORDBUSMEMORYSET(Index, Base, Length) \
55 CreateQwordField (RBUF, RB ## Index._MIN, MI ## Index) \
56 CreateQwordField (RBUF, RB ## Index._MAX, MA ## Index) \
57 CreateQwordField (RBUF, RB ## Index._LEN, LE ## Index) \
58 Store (Base, MI ## Index) \
59 Store (Length, LE ## Index) \
60 Add (MI ## Index, LE ## Index - 1, MA ## Index)
61
62DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RPIFDN", "RPI", 2)
63{
64 External (\_PR.CP00, DeviceObj)
65 External (\_PR.CP01, DeviceObj)
66 External (\_PR.CP02, DeviceObj)
67 External (\_PR.CP03, DeviceObj)
68 Scope (\_SB_)
69 {
70 include ("pep.asl")
71
72 //
73 // GPU device container describes the DMA translation required
74 // when a device behind the GPU wants to access Arm memory.
75 // Only the first GB can be addressed.
76 //
77 Device (GDV0)
78 {
79 Name (_HID, "ACPI0004")
80 Name (_UID, 0x1)
81 Name (_CCA, 0x0)
82
83 Method (_CRS, 0, Serialized) {
84 //
85 // Container devices with _DMA must have _CRS, meaning GDV0
86 // to provide all resources that GpuDevs.asl consume (except
87 // interrupts).
88 //
89 Name (RBUF, ResourceTemplate () {
90 QWORDMEMORYBUF(01)
91 QWORDMEMORYBUF(02)
92 QWORDMEMORYBUF(03)
93 // QWORDMEMORYBUF(04)
94 // QWORDMEMORYBUF(05)
95 QWORDMEMORYBUF(06)
96 QWORDMEMORYBUF(07)
97 QWORDMEMORYBUF(08)
98 QWORDMEMORYBUF(09)
99 QWORDMEMORYBUF(10)
100 QWORDMEMORYBUF(11)
101 QWORDMEMORYBUF(12)
102 QWORDMEMORYBUF(13)
103 QWORDMEMORYBUF(14)
104 QWORDMEMORYBUF(15)
105 // QWORDMEMORYBUF(16)
106 QWORDMEMORYBUF(17)
107 QWORDMEMORYBUF(18)
108 QWORDMEMORYBUF(19)
109 QWORDMEMORYBUF(20)
110 QWORDMEMORYBUF(21)
111 QWORDMEMORYBUF(22)
112 QWORDMEMORYBUF(23)
113 QWORDMEMORYBUF(24)
114 QWORDMEMORYBUF(25)
115 })
116
117 // USB
118 QWORDMEMORYSET(01, BCM2836_USB_OFFSET, BCM2836_USB_LENGTH)
119
120 // GPU
121 QWORDMEMORYSET(02, BCM2836_V3D_BUS_OFFSET, BCM2836_V3D_BUS_LENGTH)
122 QWORDMEMORYSET(03, BCM2836_HVS_OFFSET, BCM2836_HVS_LENGTH)
123 // QWORDMEMORYSET(04, BCM2836_PV0_OFFSET, BCM2836_PV0_LENGTH)
124 // QWORDMEMORYSET(05, BCM2836_PV1_OFFSET, BCM2836_PV1_LENGTH)
125 QWORDMEMORYSET(06, BCM2836_PV2_OFFSET, BCM2836_PV2_LENGTH)
126 QWORDMEMORYSET(07, BCM2836_HDMI0_OFFSET, BCM2836_HDMI0_LENGTH)
127 QWORDMEMORYSET(08, BCM2836_HDMI1_OFFSET, BCM2836_HDMI1_LENGTH)
128
129 // Mailbox
130 QWORDMEMORYSET(09, BCM2836_MBOX_OFFSET, BCM2836_MBOX_LENGTH)
131
132 // VCHIQ
133 QWORDMEMORYSET(10, BCM2836_VCHIQ_OFFSET, BCM2836_VCHIQ_LENGTH)
134
135 // GPIO
136 QWORDMEMORYSET(11, GPIO_OFFSET, GPIO_LENGTH)
137
138 // I2C
139 QWORDMEMORYSET(12, BCM2836_I2C1_OFFSET, BCM2836_I2C1_LENGTH)
140 QWORDMEMORYSET(13, BCM2836_I2C2_OFFSET, BCM2836_I2C2_LENGTH)
141
142 // SPI
143 QWORDMEMORYSET(14, BCM2836_SPI0_OFFSET, BCM2836_SPI0_LENGTH)
144 QWORDMEMORYSET(15, BCM2836_SPI1_OFFSET, BCM2836_SPI1_LENGTH)
145 // QWORDMEMORYSET(16, BCM2836_SPI2_OFFSET, BCM2836_SPI2_LENGTH)
146
147 // PWM
148 QWORDMEMORYSET(17, BCM2836_PWM_DMA_OFFSET, BCM2836_PWM_DMA_LENGTH)
149 QWORDMEMORYSET(18, BCM2836_PWM_CTRL_OFFSET, BCM2836_PWM_CTRL_LENGTH)
150 QWORDBUSMEMORYSET(19, BCM2836_PWM_BUS_BASE_ADDRESS, BCM2836_PWM_BUS_LENGTH)
151 QWORDBUSMEMORYSET(20, BCM2836_PWM_CTRL_UNCACHED_BASE_ADDRESS, BCM2836_PWM_CTRL_UNCACHED_LENGTH)
152 QWORDMEMORYSET(21, BCM2836_PWM_CLK_OFFSET, BCM2836_PWM_CLK_LENGTH)
153
154 // UART
155 QWORDMEMORYSET(22, BCM2836_PL011_UART_OFFSET, BCM2836_PL011_UART_LENGTH)
156 QWORDMEMORYSET(23, BCM2836_MINI_UART_OFFSET, BCM2836_MINI_UART_LENGTH)
157
158 // SDC
159 QWORDMEMORYSET(24, MMCHS1_OFFSET, MMCHS1_LENGTH)
160 QWORDMEMORYSET(25, SDHOST_OFFSET, SDHOST_LENGTH)
161
162 Return (RBUF)
163 }
164
165 Name (_DMA, ResourceTemplate() {
166 //
167 // Only the first GB is available.
168 // Bus 0xC0000000 -> CPU 0x00000000.
169 //
170 QWordMemory (ResourceProducer,
171 ,
172 MinFixed,
173 MaxFixed,
174 NonCacheable,
175 ReadWrite,
176 0x0,
177 0x00000000C0000000, // MIN
178 0x00000000FFFFFFFF, // MAX
179 0xFFFFFFFF40000000, // TRA
180 0x0000000040000000, // LEN
181 ,
182 ,
183 )
184 })
185#include "gpudevs.asl"
186 }
187
188#if defined(CONFIG_TARGET_RPI_4)
189 Device (ETH0)
190 {
191 Name (_HID, "BCM6E4E")
192 Name (_CID, "BCM6E4E")
193 Name (_UID, 0x0)
194 Name (_CCA, 0x0)
195
196 Method (_CRS, 0x0, Serialized)
197 {
198 Return (ResourceTemplate ()
199 {
200 // No need for MEMORY32SETBASE on Genet as we have a straight base address constant
201 MEMORY32FIXED (ReadWrite, GENET_BASE_ADDRESS, GENET_LENGTH, )
202 Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { GENET_INTERRUPT0, GENET_INTERRUPT1 }
203 })
204 }
205 Name (_DSD, Package () {
206 ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
207 Package () {
208 Package () { "brcm,max-dma-burst-size", 0x08 },
209 Package () { "phy-mode", "rgmii-rxid" },
210 }
211 })
212 }
213
214 // Define a simple thermal zone. The idea here is we compute the SOC temp
215 // via a register we can read, and give it to the OS. This enables basic
216 // reports from the "sensors" utility, and the OS can then poll and take
217 // actions if that temp exceeds any of the given thresholds.
218 Device (EC00)
219 {
220 Name (_HID, EISAID ("PNP0C06"))
221 Name (_CCA, 0x0)
222
223 // all temps in are tenths of K (aka 2732 is the min temps in Linux (aka 0C))
224 ThermalZone (TZ00) {
225 OperationRegion (TEMS, SystemMemory, THERM_SENSOR_BASE_ADDRESS, THERM_SENSOR_LENGTH)
226 Field (TEMS, DWordAcc, NoLock, Preserve) {
227 TMPS, 32
228 }
229 Method (_TMP, 0, Serialized) {
230 return (((410040 - ((TMPS & 0x3ff) * 487)) / 100) + 2732);
231 }
232
233 Method (_SCP, 3) { } // receive cooling policy from OS
234
235 Method (_CRT) { Return (3632) } // (90C) Critical temp point (immediate power-off)
236 Method (_HOT) { Return (3582) } // (85C) HOT state where OS should hibernate
237 Method (_PSV) { Return (3532) } // (80C) Passive cooling (CPU throttling) trip point
238
239 // SSDT inserts _AC0/_AL0 @60C here, if a FAN is configured
240
241 Name (_TZP, 10) //The OSPM must poll this device every 1 seconds
242 Name (_PSL, Package () { \_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03 })
243 }
244 }
245#endif
246
247
248#include "uart.asl"
249#include "rhpx.asl"
250#include "sdhc.asl"
251#include "emmc.asl"
252#include "pci.asl"
253 }
254}