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git01.mediatek.com / filogic / uboot / dca22e5eda0d0148c42970b29d7f4019e9742cc3 / . / arch / arm / dts / nuvoton-npcm8xx-u-boot.dtsi
blob: be2ad0cf6cd097a19835a8bf866939535ffbc32d [file] [log] [blame]
Jim Liu147c0002022-09-27 16:45:15 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2
3#include <dt-bindings/reset/nuvoton,npcm8xx-reset.h>
4
5/ {
6 #address-cells = <1>;
7 #size-cells = <1>;
8 interrupt-parent = <&gic>;
9
10 /* external reference clock */
11 clk_refclk: clk-refclk {
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <25000000>;
15 clock-output-names = "refclk";
16 };
17
18 ahb {
19 rstc: reset-controller@f0801000 {
20 compatible = "nuvoton,npcm845-reset", "syscon",
21 "simple-mfd";
22 reg = <0x0 0xf0801000 0x0 0xC4>;
23 rstc1: reset-controller1 {
24 compatible = "syscon-reset";
25 #reset-cells = <1>;
26 regmap = <&rstc>;
27 offset = <NPCM8XX_RESET_IPSRST1>;
28 mask = <0xFFFFFFFF>;
29 };
30 rstc2: reset-controller2 {
31 compatible = "syscon-reset";
32 #reset-cells = <1>;
33 regmap = <&rstc>;
34 offset = <NPCM8XX_RESET_IPSRST2>;
35 mask = <0xFFFFFFFF>;
36 };
37 rstc3: reset-controller3 {
38 compatible = "syscon-reset";
39 #reset-cells = <1>;
40 regmap = <&rstc>;
41 offset = <NPCM8XX_RESET_IPSRST3>;
42 mask = <0xFFFFFFFF>;
43 };
44 rstc4: reset-controller4 {
45 compatible = "syscon-reset";
46 #reset-cells = <1>;
47 regmap = <&rstc>;
48 offset = <NPCM8XX_RESET_IPSRST4>;
49 mask = <0xFFFFFFFF>;
50 };
51 };
52
53 clk: clock-controller@f0801000 {
54 compatible = "nuvoton,npcm845-clk", "syscon";
55 #clock-cells = <1>;
56 clock-controller;
57 reg = <0x0 0xf0801000 0x0 0x1000>;
58 clock-names = "refclk";
59 clocks = <&clk_refclk>;
60 };
61
Jim Liu2e4fb4e2023-01-17 16:59:21 +0800[diff] [blame]62 gmac0: eth@f0802000 {
63 device_type = "network";
64 compatible = "nuvoton,npcm-dwmac", "st,stm32-dwmac";
65 reg = <0x0 0xf0802000 0x0 0x2000>,
66 <0x0 0xf0780000 0x0 0x200>;
67 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
68 interrupt-names = "macirq";
69 clocks = <&clk NPCM8XX_CLK_AHB>;
70 clock-names = "stmmaceth";
71 pinctrl-names = "default";
72 pinctrl-0 = <&rg1mdio_pins>;
73 resets = <&rstc2 NPCM8XX_RESET_GMAC1>;
74 status = "disabled";
75 };
76
77 gmac1: eth@f0804000 {
78 device_type = "network";
79 compatible = "nuvoton,npcm-dwmac", "st,stm32-dwmac";
80 reg = <0x0 0xf0804000 0x0 0x2000>;
81 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
82 interrupt-names = "macirq";
83 clocks = <&clk NPCM8XX_CLK_AHB>;
84 clock-names = "stmmaceth";
85 pinctrl-names = "default";
86 pinctrl-0 = <&rg2_pins
87 &rg2mdio_pins>;
88 resets = <&rstc2 NPCM8XX_RESET_GMAC2>;
89 status = "disabled";
90 };
91
92 gmac2: eth@f0806000 {
93 device_type = "network";
94 compatible = "nuvoton,npcm-dwmac", "st,stm32-dwmac";
95 reg = <0x0 0xf0806000 0x0 0x2000>;
96 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
97 interrupt-names = "macirq";
98 clocks = <&clk NPCM8XX_CLK_AHB>;
99 clock-names = "stmmaceth";
100 pinctrl-names = "default";
101 pinctrl-0 = <&r1_pins
102 &r1err_pins
103 &r1md_pins>;
104 resets = <&rstc1 NPCM8XX_RESET_GMAC3>;
105 status = "disabled";
106 };
107
108 gmac3: eth@f0808000 {
109 device_type = "network";
110 compatible = "nuvoton,npcm-dwmac", "st,stm32-dwmac";
111 reg = <0x0 0xf0808000 0x0 0x2000>;
112 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
113 interrupt-names = "macirq";
114 clocks = <&clk NPCM8XX_CLK_AHB>;
115 clock-names = "stmmaceth";
116 pinctrl-names = "default";
117 pinctrl-0 = <&r2_pins
118 &r2err_pins
119 &r2md_pins>;
120 resets = <&rstc1 NPCM8XX_RESET_GMAC4>;
121 status = "disabled";
122 };
123
Jim Liu89b26542022-11-28 10:32:44 +0800[diff] [blame]124 ehci1: usb@f0828100 {
125 compatible = "nuvoton,npcm845-ehci";
126 reg = <0x0 0xf0828100 0x0 0x1000>;
127 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
128 resets = <&rstc2 NPCM8XX_RESET_USBH1>;
129 status = "disabled";
130 };
131
132 ehci2: usb@f082a100 {
133 compatible = "nuvoton,npcm845-ehci";
134 reg = <0x0 0xf082a100 0x0 0x1000>;
135 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
136 resets = <&rstc4 NPCM8XX_RESET_USBH2>;
137 status = "disabled";
138 };
139
140 ohci1: usb@f0829000 {
141 compatible = "nuvoton,npcm845-ohci";
142 reg = <0x0 0xF0829000 0x0 0x1000>;
143 resets = <&rstc2 NPCM8XX_RESET_USBH1>;
144 status = "disabled";
145 };
146
147 ohci2: usb@f082b000 {
148 compatible = "nuvoton,npcm845-ohci";
149 reg = <0x0 0xF082B000 0x0 0x1000>;
150 resets = <&rstc4 NPCM8XX_RESET_USBH2>;
151 status = "disabled";
152 };
153
154 usbphy {
155 compatible = "simple-bus";
156 #address-cells = <1>;
157 #size-cells = <0>;
158 syscon = <&gcr>;
159 usbphy1: usbphy@1 {
160 compatible = "nuvoton,npcm845-usb-phy";
161 #phy-cells = <1>;
162 reg = <1>;
163 resets = <&rstc3 NPCM8XX_RESET_USBPHY1>;
164 status = "disabled";
165 };
166 usbphy2: usbphy@2 {
167 compatible = "nuvoton,npcm845-usb-phy";
168 #phy-cells = <1>;
169 reg = <2>;
170 resets = <&rstc3 NPCM8XX_RESET_USBPHY2>;
171 status = "disabled";
172 };
173 usbphy3: usbphy@3 {
174 compatible = "nuvoton,npcm845-usb-phy";
175 #phy-cells = <1>;
176 reg = <3>;
177 resets = <&rstc3 NPCM8XX_RESET_USBPHY3>;
178 status = "disabled";
179 };
180 };
181
182 udc0:udc@f0830100 {
183 compatible = "nuvoton,npcm845-udc";
184 reg = <0x0 0xf0830100 0x0 0x100
185 0x0 0xfffb0000 0x0 0x800>;
186 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
187 clocks = <&clk NPCM8XX_CLK_SU>;
188 clock-names = "clk_usb_bridge";
189 resets = <&rstc3 NPCM8XX_RESET_UDC0>;
190 status = "disable";
191 };
192
193 udc1:udc@f0831100 {
194 compatible = "nuvoton,npcm845-udc";
195 reg = <0x0 0xf0831100 0x0 0x100
196 0x0 0xfffb0800 0x0 0x800>;
197 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
198 clocks = <&clk NPCM8XX_CLK_SU>;
199 clock-names = "clk_usb_bridge";
200 resets = <&rstc1 NPCM8XX_RESET_UDC1>;
201 status = "disable";
202 };
203
204 udc2:udc@f0832100 {
205 compatible = "nuvoton,npcm845-udc";
206 reg = <0x0 0xf0832100 0x0 0x100
207 0x0 0xfffb1000 0x0 0x800>;
208 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
209 clocks = <&clk NPCM8XX_CLK_SU>;
210 clock-names = "clk_usb_bridge";
211 resets = <&rstc1 NPCM8XX_RESET_UDC2>;
212 status = "disable";
213 };
214
215 udc3:udc@f0833100 {
216 compatible = "nuvoton,npcm845-udc";
217 reg = <0x0 0xf0833100 0x0 0x100
218 0x0 0xfffb1800 0x0 0x800>;
219 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
220 clocks = <&clk NPCM8XX_CLK_SU>;
221 clock-names = "clk_usb_bridge";
222 resets = <&rstc1 NPCM8XX_RESET_UDC3>;
223 status = "disable";
224 };
225
226 udc4:udc@f0834100 {
227 compatible = "nuvoton,npcm845-udc";
228 reg = <0x0 0xf0834100 0x0 0x100
229 0x0 0xfffb2000 0x0 0x800>;
230 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
231 clocks = <&clk NPCM8XX_CLK_SU>;
232 clock-names = "clk_usb_bridge";
233 resets = <&rstc1 NPCM8XX_RESET_UDC4>;
234 status = "disable";
235 };
236
237 udc5:udc@f0835100 {
238 compatible = "nuvoton,npcm845-udc";
239 reg = <0x0 0xf0835100 0x0 0x100
240 0x0 0xfffb2800 0x0 0x800>;
241 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
242 clocks = <&clk NPCM8XX_CLK_SU>;
243 clock-names = "clk_usb_bridge";
244 resets = <&rstc1 NPCM8XX_RESET_UDC5>;
245 status = "disable";
246 };
247
248 udc6:udc@f0836100 {
249 compatible = "nuvoton,npcm845-udc";
250 reg = <0x0 0xf0836100 0x0 0x100
251 0x0 0xfffb3000 0x0 0x800>;
252 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&clk NPCM8XX_CLK_SU>;
254 clock-names = "clk_usb_bridge";
255 resets = <&rstc1 NPCM8XX_RESET_UDC6>;
256 status = "disable";
257 };
258
259 udc7:udc@f0837100 {
260 compatible = "nuvoton,npcm845-udc";
261 reg = <0x0 0xf0837100 0x0 0x100
262 0x0 0xfffb3800 0x0 0x800>;
263 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
264 clocks = <&clk NPCM8XX_CLK_SU>;
265 clock-names = "clk_usb_bridge";
266 resets = <&rstc3 NPCM8XX_RESET_UDC7>;
267 status = "disable";
268 };
269
270 udc8:udc@f0838100 {
271 compatible = "nuvoton,npcm845-udc";
272 reg = <0x0 0xf0838100 0x0 0x100
273 0x0 0xfffb4000 0x0 0x800>;
274 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
275 clocks = <&clk NPCM8XX_CLK_SU>;
276 clock-names = "clk_usb_bridge";
277 resets = <&rstc3 NPCM8XX_RESET_UDC8>;
278 status = "disable";
279 };
280
281 udc9:udc@f0839100 {
282 compatible = "nuvoton,npcm845-udc";
283 reg = <0x0 0xf0839100 0x0 0x100
284 0x0 0xfffb4800 0x0 0x800>;
285 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&clk NPCM8XX_CLK_SU>;
287 clock-names = "clk_usb_bridge";
288 resets = <&rstc3 NPCM8XX_RESET_UDC9>;
289 status = "disable";
290 };
291
Jim Liu147c0002022-09-27 16:45:15 +0800[diff] [blame]292 apb {
293 serial0: serial@0 {
294 compatible = "nuvoton,npcm845-uart";
295 reg = <0x0 0x1000>;
296 clocks = <&clk NPCM8XX_CLK_UART>, <&clk NPCM8XX_CLK_PLL2DIV2>;
297 clock-frequency = <24000000>;
298 status = "disabled";
299 };
300
Jim Liu2e4fb4e2023-01-17 16:59:21 +0800[diff] [blame]301 serial1: serial@1000 {
302 compatible = "nuvoton,npcm845-uart";
303 reg = <0x1000 0x1000>;
304 clocks = <&clk NPCM8XX_CLK_UART>, <&clk NPCM8XX_CLK_PLL2DIV2>;
305 status = "disabled";
306 };
307
308 serial2: serial@2000 {
309 compatible = "nuvoton,npcm845-uart";
310 reg = <0x2000 0x1000>;
311 clocks = <&clk NPCM8XX_CLK_UART>, <&clk NPCM8XX_CLK_PLL2DIV2>;
312 status = "disabled";
313 };
314
315 serial3: serial@3000 {
316 compatible = "nuvoton,npcm845-uart";
317 reg = <0x3000 0x1000>;
318 clocks = <&clk NPCM8XX_CLK_UART>, <&clk NPCM8XX_CLK_PLL2DIV2>;
319 status = "disabled";
320 };
321
322 serial4: serial@4000 {
323 compatible = "nuvoton,npcm845-uart";
324 reg = <0x4000 0x1000>;
325 clocks = <&clk NPCM8XX_CLK_UART2>, <&clk NPCM8XX_CLK_PLL2DIV2>;
326 status = "disabled";
327 };
328
329 serial5: serial@5000 {
330 compatible = "nuvoton,npcm845-uart";
331 reg = <0x5000 0x1000>;
332 clocks = <&clk NPCM8XX_CLK_UART2>, <&clk NPCM8XX_CLK_PLL2DIV2>;
333 status = "disabled";
334 };
335
336 serial6: serial@6000 {
337 compatible = "nuvoton,npcm845-uart";
338 reg = <0x6000 0x1000>;
339 clocks = <&clk NPCM8XX_CLK_UART2>, <&clk NPCM8XX_CLK_PLL2DIV2>;
340 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
341 status = "disabled";
342 };
343
Jim Liu147c0002022-09-27 16:45:15 +0800[diff] [blame]344 gpio0: gpio0@10000 {
Jim Liu89b26542022-11-28 10:32:44 +0800[diff] [blame]345 compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
Jim Liu147c0002022-09-27 16:45:15 +0800[diff] [blame]346 reg = <0x10000 0xB0>;
347 #gpio-cells = <2>;
348 gpio-controller;
349 gpio-bank-name = "gpio0";
350 };
351
352 gpio1: gpio1@11000 {
Jim Liu89b26542022-11-28 10:32:44 +0800[diff] [blame]353 compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
Jim Liu147c0002022-09-27 16:45:15 +0800[diff] [blame]354 reg = <0x11000 0xB0>;
355 #gpio-cells = <2>;
356 gpio-controller;
357 gpio-bank-name = "gpio1";
358 };
359
360 gpio2: gpio2@12000 {
Jim Liu89b26542022-11-28 10:32:44 +0800[diff] [blame]361 compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
Jim Liu147c0002022-09-27 16:45:15 +0800[diff] [blame]362 reg = <0x12000 0xB0>;
363 #gpio-cells = <2>;
364 gpio-controller;
365 gpio-bank-name = "gpio2";
366 };
367
368 gpio3: gpio3@13000 {
Jim Liu89b26542022-11-28 10:32:44 +0800[diff] [blame]369 compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
Jim Liu147c0002022-09-27 16:45:15 +0800[diff] [blame]370 reg = <0x13000 0xB0>;
371 #gpio-cells = <2>;
372 gpio-controller;
373 gpio-bank-name = "gpio3";
374 };
375
376 gpio4: gpio4@14000 {
Jim Liu89b26542022-11-28 10:32:44 +0800[diff] [blame]377 compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
Jim Liu147c0002022-09-27 16:45:15 +0800[diff] [blame]378 reg = <0x14000 0xB0>;
379 #gpio-cells = <2>;
380 gpio-controller;
381 gpio-bank-name = "gpio4";
382 };
383
384 gpio5: gpio5@15000 {
Jim Liu89b26542022-11-28 10:32:44 +0800[diff] [blame]385 compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
Jim Liu147c0002022-09-27 16:45:15 +0800[diff] [blame]386 reg = <0x15000 0xB0>;
387 #gpio-cells = <2>;
388 gpio-controller;
389 gpio-bank-name = "gpio5";
390 };
391
392 gpio6: gpio6@16000 {
Jim Liu89b26542022-11-28 10:32:44 +0800[diff] [blame]393 compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
Jim Liu147c0002022-09-27 16:45:15 +0800[diff] [blame]394 reg = <0x16000 0xB0>;
395 #gpio-cells = <2>;
396 gpio-controller;
397 gpio-bank-name = "gpio6";
398 };
399
400 gpio7: gpio7@17000 {
Jim Liu89b26542022-11-28 10:32:44 +0800[diff] [blame]401 compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
Jim Liu147c0002022-09-27 16:45:15 +0800[diff] [blame]402 reg = <0x17000 0xB0>;
403 #gpio-cells = <2>;
404 gpio-controller;
405 gpio-bank-name = "gpio7";
406 };
Jim Liu2e4fb4e2023-01-17 16:59:21 +0800[diff] [blame]407
408 rng: rng@b000 {
409 compatible = "nuvoton,npcm845-rng";
410 reg = <0xb000 0x8>;
411 status = "disabled";
412 };
413
414 otp: otp@189000 {
415 compatible = "nuvoton,npcm845-otp";
416 reg = <0x189000 0x1000>;
417 status = "disabled";
418 };
419
420 aes: aes@f0858000 {
421 compatible = "nuvoton,npcm845-aes";
422 reg = <0x0 0xf0858000 0x0 0x1000>,
423 <0x0 0xf0851000 0x0 0x1000>;
424 status = "disabled";
425 clocks = <&clk NPCM8XX_CLK_AHB>;
426 clock-names = "clk_ahb";
427 };
428
429 sha:sha@f085a000 {
430 compatible = "nuvoton,npcm845-sha";
431 reg = <0x0 0xf085a000 0x0 0x1000>;
432 status = "disabled";
433 clocks = <&clk NPCM8XX_CLK_AHB>;
434 clock-names = "clk_ahb";
435 };
Jim Liu147c0002022-09-27 16:45:15 +0800[diff] [blame]436 };
437 };
Jim Liu89b26542022-11-28 10:32:44 +0800[diff] [blame]438 pinctrl: pinctrl@f0800000 {
439 compatible = "nuvoton,npcm845-pinctrl", "syscon", "simple-mfd";
440 reg = <0x0 0xf0010000 0x0 0x8000>;
441 syscon-gcr = <&gcr>;
442 syscon-rst = <&rstc>;
443 status = "okay";
444
445 iox1_pins: iox1-pins {
446 groups = "iox1";
447 function = "iox1";
448 };
449 iox2_pins: iox2-pins {
450 groups = "iox2";
451 function = "iox2";
452 };
453 smb1d_pins: smb1d-pins {
454 groups = "smb1d";
455 function = "smb1d";
456 };
457 smb2d_pins: smb2d-pins {
458 groups = "smb2d";
459 function = "smb2d";
460 };
461 lkgpo1_pins: lkgpo1-pins {
462 groups = "lkgpo1";
463 function = "lkgpo1";
464 };
465 lkgpo2_pins: lkgpo2-pins {
466 groups = "lkgpo2";
467 function = "lkgpo2";
468 };
469 ioxh_pins: ioxh-pins {
470 groups = "ioxh";
471 function = "ioxh";
472 };
473 gspi_pins: gspi-pins {
474 groups = "gspi";
475 function = "gspi";
476 };
477 smb5b_pins: smb5b-pins {
478 groups = "smb5b";
479 function = "smb5b";
480 };
481 smb5c_pins: smb5c-pins {
482 groups = "smb5c";
483 function = "smb5c";
484 };
485 lkgpo0_pins: lkgpo0-pins {
486 groups = "lkgpo0";
487 function = "lkgpo0";
488 };
489 pspi_pins: pspi-pins {
490 groups = "pspi";
491 function = "pspi";
492 };
493 vgadig_pins: vgadig-pins {
494 groups = "vgadig";
495 function = "vgadig";
496 };
497 jm1_pins: jm1-pins {
498 groups = "jm1";
499 function = "jm1";
500 };
501 jm2_pins: jm2-pins {
502 groups = "jm2";
503 function = "jm2";
504 };
505 smb4b_pins: smb4b-pins {
506 groups = "smb4b";
507 function = "smb4b";
508 };
509 smb4c_pins: smb4c-pins {
510 groups = "smb4c";
511 function = "smb4c";
512 };
513 smb15_pins: smb15-pins {
514 groups = "smb15";
515 function = "smb15";
516 };
517 smb16_pins: smb16-pins {
518 groups = "smb16";
519 function = "smb16";
520 };
521 smb17_pins: smb17-pins {
522 groups = "smb17";
523 function = "smb17";
524 };
525 smb18_pins: smb18-pins {
526 groups = "smb18";
527 function = "smb18";
528 };
529 smb19_pins: smb19-pins {
530 groups = "smb19";
531 function = "smb19";
532 };
533 smb20_pins: smb20-pins {
534 groups = "smb20";
535 function = "smb20";
536 };
537 smb21_pins: smb21-pins {
538 groups = "smb21";
539 function = "smb21";
540 };
541 smb22_pins: smb22-pins {
542 groups = "smb22";
543 function = "smb22";
544 };
545 smb23_pins: smb23-pins {
546 groups = "smb23";
547 function = "smb23";
548 };
549 smb4d_pins: smb4d-pins {
550 groups = "smb4d";
551 function = "smb4d";
552 };
553 smb14_pins: smb14-pins {
554 groups = "smb14";
555 function = "smb14";
556 };
557 smb5_pins: smb5-pins {
558 groups = "smb5";
559 function = "smb5";
560 };
561 smb4_pins: smb4-pins {
562 groups = "smb4";
563 function = "smb4";
564 };
565 smb3_pins: smb3-pins {
566 groups = "smb3";
567 function = "smb3";
568 };
569 spi0cs1_pins: spi0cs1-pins {
570 groups = "spi0cs1";
571 function = "spi0cs1";
572 };
573 spi0cs2_pins: spi0cs2-pins {
574 groups = "spi0cs2";
575 function = "spi0cs2";
576 };
577 spi0cs3_pins: spi0cs3-pins {
578 groups = "spi0cs3";
579 function = "spi0cs3";
580 };
581 smb3c_pins: smb3c-pins {
582 groups = "smb3c";
583 function = "smb3c";
584 };
585 smb3b_pins: smb3b-pins {
586 groups = "smb3b";
587 function = "smb3b";
588 };
589 hsi1a_pins: hsi1a-pins {
590 groups = "hsi1a";
591 function = "hsi1a";
592 };
593 hsi1b_pins: hsi1b-pins {
594 groups = "hsi1b";
595 function = "hsi1b";
596 };
597 hsi1c_pins: hsi1c-pins {
598 groups = "hsi1c";
599 function = "hsi1c";
600 };
601 hsi2a_pins: hsi2a-pins {
602 groups = "hsi2a";
603 function = "hsi2a";
604 };
605 hsi2b_pins: hsi2b-pins {
606 groups = "hsi2b";
607 function = "hsi2b";
608 };
609 hsi2c_pins: hsi2c-pins {
610 groups = "hsi2c";
611 function = "hsi2c";
612 };
613 bmcuart0a_pins: bmcuart0a-pins {
614 groups = "bmcuart0a";
615 function = "bmcuart0a";
616 };
617 bmcuart0b_pins: bmcuart0b-pins {
618 groups = "bmcuart0b";
619 function = "bmcuart0b";
620 };
621 bmcuart1_pins: bmcuart1-pins {
622 groups = "bmcuart1";
623 function = "bmcuart1";
624 };
625 bu4_pins: bu4-pins {
626 groups = "bu4";
627 function = "bu4";
628 };
629 bu5_pins: bu5-pins {
630 groups = "bu5";
631 function = "bu5";
632 };
633 bu6_pins: bu6-pins {
634 groups = "bu6";
635 function = "bu6";
636 };
637 r1err_pins: r1err-pins {
638 groups = "r1err";
639 function = "r1err";
640 };
641 r1md_pins: r1md-pins {
642 groups = "r1md";
643 function = "r1md";
644 };
645 r1oen_pins: r1oen-pins {
646 groups = "r1oen";
647 function = "r1oen";
648 };
649 r1en_pins: r1en-pins {
650 groups = "r1en";
651 function = "r1en";
652 };
653 r2oen_pins: r2oen-pins {
654 groups = "r2oen";
655 function = "r2oen";
656 };
657 r2en_pins: r2en-pins {
658 groups = "r2en";
659 function = "r2en";
660 };
661 rmii3_pins: rmii3_pins {
662 groups = "rmii3";
663 function = "rmii3";
664 };
665 r3oen_pins: r3oen-pins {
666 groups = "r3oen";
667 function = "r3oen";
668 };
669 r3en_pins: r3en-pins {
670 groups = "r3en";
671 function = "r3en";
672 };
673 smb3d_pins: smb3d-pins {
674 groups = "smb3d";
675 function = "smb3d";
676 };
677 fanin0_pins: fanin0-pins {
678 groups = "fanin0";
679 function = "fanin0";
680 };
681 fanin1_pins: fanin1-pins {
682 groups = "fanin1";
683 function = "fanin1";
684 };
685 fanin2_pins: fanin2-pins {
686 groups = "fanin2";
687 function = "fanin2";
688 };
689 fanin3_pins: fanin3-pins {
690 groups = "fanin3";
691 function = "fanin3";
692 };
693 fanin4_pins: fanin4-pins {
694 groups = "fanin4";
695 function = "fanin4";
696 };
697 fanin5_pins: fanin5-pins {
698 groups = "fanin5";
699 function = "fanin5";
700 };
701 fanin6_pins: fanin6-pins {
702 groups = "fanin6";
703 function = "fanin6";
704 };
705 fanin7_pins: fanin7-pins {
706 groups = "fanin7";
707 function = "fanin7";
708 };
709 fanin8_pins: fanin8-pins {
710 groups = "fanin8";
711 function = "fanin8";
712 };
713 fanin9_pins: fanin9-pins {
714 groups = "fanin9";
715 function = "fanin9";
716 };
717 fanin10_pins: fanin10-pins {
718 groups = "fanin10";
719 function = "fanin10";
720 };
721 fanin11_pins: fanin11-pins {
722 groups = "fanin11";
723 function = "fanin11";
724 };
725 fanin12_pins: fanin12-pins {
726 groups = "fanin12";
727 function = "fanin12";
728 };
729 fanin13_pins: fanin13-pins {
730 groups = "fanin13";
731 function = "fanin13";
732 };
733 fanin14_pins: fanin14-pins {
734 groups = "fanin14";
735 function = "fanin14";
736 };
737 fanin15_pins: fanin15-pins {
738 groups = "fanin15";
739 function = "fanin15";
740 };
741 pwm0_pins: pwm0-pins {
742 groups = "pwm0";
743 function = "pwm0";
744 };
745 pwm1_pins: pwm1-pins {
746 groups = "pwm1";
747 function = "pwm1";
748 };
749 pwm2_pins: pwm2-pins {
750 groups = "pwm2";
751 function = "pwm2";
752 };
753 pwm3_pins: pwm3-pins {
754 groups = "pwm3";
755 function = "pwm3";
756 };
757 r2_pins: r2-pins {
758 groups = "r2";
759 function = "r2";
760 };
761 r2err_pins: r2err-pins {
762 groups = "r2err";
763 function = "r2err";
764 };
765 r2md_pins: r2md-pins {
766 groups = "r2md";
767 function = "r2md";
768 };
769 r3rxer_pins: r3rxer_pins {
770 groups = "r3rxer";
771 function = "r3rxer";
772 };
773 ga20kbc_pins: ga20kbc-pins {
774 groups = "ga20kbc";
775 function = "ga20kbc";
776 };
777 smb5d_pins: smb5d-pins {
778 groups = "smb5d";
779 function = "smb5d";
780 };
781 lpc_pins: lpc-pins {
782 groups = "lpc";
783 function = "lpc";
784 };
785 espi_pins: espi-pins {
786 groups = "espi";
787 function = "espi";
788 };
789 rg1_pins: rg1-pins {
790 groups = "rg1";
791 function = "rg1";
792 };
793 rg1mdio_pins: rg1mdio-pins {
794 groups = "rg1mdio";
795 function = "rg1mdio";
796 };
797 rg2_pins: rg2-pins {
798 groups = "rg2";
799 function = "rg2";
800 };
801 ddr_pins: ddr-pins {
802 groups = "ddr";
803 function = "ddr";
804 };
805 i3c0_pins: i3c0-pins {
806 groups = "i3c0";
807 function = "i3c0";
808 };
809 i3c1_pins: i3c1-pins {
810 groups = "i3c1";
811 function = "i3c1";
812 };
813 i3c2_pins: i3c2-pins {
814 groups = "i3c2";
815 function = "i3c2";
816 };
817 i3c3_pins: i3c3-pins {
818 groups = "i3c3";
819 function = "i3c3";
820 };
821 i3c4_pins: i3c4-pins {
822 groups = "i3c4";
823 function = "i3c4";
824 };
825 i3c5_pins: i3c5-pins {
826 groups = "i3c5";
827 function = "i3c5";
828 };
829 smb0_pins: smb0-pins {
830 groups = "smb0";
831 function = "smb0";
832 };
833 smb1_pins: smb1-pins {
834 groups = "smb1";
835 function = "smb1";
836 };
837 smb2_pins: smb2-pins {
838 groups = "smb2";
839 function = "smb2";
840 };
841 smb2c_pins: smb2c-pins {
842 groups = "smb2c";
843 function = "smb2c";
844 };
845 smb2b_pins: smb2b-pins {
846 groups = "smb2b";
847 function = "smb2b";
848 };
849 smb1c_pins: smb1c-pins {
850 groups = "smb1c";
851 function = "smb1c";
852 };
853 smb1b_pins: smb1b-pins {
854 groups = "smb1b";
855 function = "smb1b";
856 };
857 smb8_pins: smb8-pins {
858 groups = "smb8";
859 function = "smb8";
860 };
861 smb9_pins: smb9-pins {
862 groups = "smb9";
863 function = "smb9";
864 };
865 smb10_pins: smb10-pins {
866 groups = "smb10";
867 function = "smb10";
868 };
869 smb11_pins: smb11-pins {
870 groups = "smb11";
871 function = "smb11";
872 };
873 sd1_pins: sd1-pins {
874 groups = "sd1";
875 function = "sd1";
876 };
877 sd1pwr_pins: sd1pwr-pins {
878 groups = "sd1pwr";
879 function = "sd1pwr";
880 };
881 pwm4_pins: pwm4-pins {
882 groups = "pwm4";
883 function = "pwm4";
884 };
885 pwm5_pins: pwm5-pins {
886 groups = "pwm5";
887 function = "pwm5";
888 };
889 pwm6_pins: pwm6-pins {
890 groups = "pwm6";
891 function = "pwm6";
892 };
893 pwm7_pins: pwm7-pins {
894 groups = "pwm7";
895 function = "pwm7";
896 };
897 pwm8_pins: pwm8-pins {
898 groups = "pwm8";
899 function = "pwm8";
900 };
901 pwm9_pins: pwm9-pins {
902 groups = "pwm9";
903 function = "pwm9";
904 };
905 pwm10_pins: pwm10-pins {
906 groups = "pwm10";
907 function = "pwm10";
908 };
909 pwm11_pins: pwm11-pins {
910 groups = "pwm11";
911 function = "pwm11";
912 };
913 mmc8_pins: mmc8-pins {
914 groups = "mmc8";
915 function = "mmc8";
916 };
917 mmc_pins: mmc-pins {
918 groups = "mmc";
919 function = "mmc";
920 };
921 mmcwp_pins: mmcwp-pins {
922 groups = "mmcwp";
923 function = "mmcwp";
924 };
925 mmccd_pins: mmccd-pins {
926 groups = "mmccd";
927 function = "mmccd";
928 };
929 mmcrst_pins: mmcrst-pins {
930 groups = "mmcrst";
931 function = "mmcrst";
932 };
933 clkout_pins: clkout-pins {
934 groups = "clkout";
935 function = "clkout";
936 };
937 serirq_pins: serirq-pins {
938 groups = "serirq";
939 function = "serirq";
940 };
941 scipme_pins: scipme-pins {
942 groups = "scipme";
943 function = "scipme";
944 };
945 sci_pins: sci-pins {
946 groups = "sci";
947 function = "sci";
948 };
949 smb6_pins: smb6-pins {
950 groups = "smb6";
951 function = "smb6";
952 };
953 smb7_pins: smb7-pins {
954 groups = "smb7";
955 function = "smb7";
956 };
957 spi1_pins: spi1-pins {
958 groups = "spi1";
959 function = "spi1";
960 };
961 spi1d23_pins: spi1d23-pins {
962 groups = "spi1d23";
963 function = "spi1d23";
964 };
965 faninx_pins: faninx-pins {
966 groups = "faninx";
967 function = "faninx";
968 };
969 r1_pins: r1-pins {
970 groups = "r1";
971 function = "r1";
972 };
973 spi3_pins: spi3-pins {
974 groups = "spi3";
975 function = "spi3";
976 };
977 spi3cs1_pins: spi3cs1-pins {
978 groups = "spi3cs1";
979 function = "spi3cs1";
980 };
981 spi3quad_pins: spi3quad-pins {
982 groups = "spi3quad";
983 function = "spi3quad";
984 };
985 spi3cs2_pins: spi3cs2-pins {
986 groups = "spi3cs2";
987 function = "spi3cs2";
988 };
989 spi3cs3_pins: spi3cs3-pins {
990 groups = "spi3cs3";
991 function = "spi3cs3";
992 };
993 nprd_smi_pins: nprd-smi-pins {
994 groups = "nprd_smi";
995 function = "nprd_smi";
996 };
997 smb0b_pins: smb0b-pins {
998 groups = "smb0b";
999 function = "smb0b";
1000 };
1001 smb0c_pins: smb0c-pins {
1002 groups = "smb0c";
1003 function = "smb0c";
1004 };
1005 smb0den_pins: smb0den-pins {
1006 groups = "smb0den";
1007 function = "smb0den";
1008 };
1009 smb0d_pins: smb0d-pins {
1010 groups = "smb0d";
1011 function = "smb0d";
1012 };
1013 rg2mdio_pins: rg2mdio-pins {
1014 groups = "rg2mdio";
1015 function = "rg2mdio";
1016 };
1017 rg2refck_pins: rg2refck-pins {
1018 groups = "rg2refck";
1019 function = "rg2refck";
1020 };
1021 wdog1_pins: wdog1-pins {
1022 groups = "wdog1";
1023 function = "wdog1";
1024 };
1025 wdog2_pins: wdog2-pins {
1026 groups = "wdog2";
1027 function = "wdog2";
1028 };
1029 smb12_pins: smb12-pins {
1030 groups = "smb12";
1031 function = "smb12";
1032 };
1033 smb13_pins: smb13-pins {
1034 groups = "smb13";
1035 function = "smb13";
1036 };
1037 spix_pins: spix-pins {
1038 groups = "spix";
1039 function = "spix";
1040 };
1041 spixcs1_pins: spixcs1-pins {
1042 groups = "spixcs1";
1043 function = "spixcs1";
1044 };
1045 clkreq_pins: clkreq-pins {
1046 groups = "clkreq";
1047 function = "clkreq";
1048 };
1049 hgpio0_pins: hgpio0-pins {
1050 groups = "hgpio0";
1051 function = "hgpio0";
1052 };
1053 hgpio1_pins: hgpio1-pins {
1054 groups = "hgpio1";
1055 function = "hgpio1";
1056 };
1057 hgpio2_pins: hgpio2-pins {
1058 groups = "hgpio2";
1059 function = "hgpio2";
1060 };
1061 hgpio3_pins: hgpio3-pins {
1062 groups = "hgpio3";
1063 function = "hgpio3";
1064 };
1065 hgpio4_pins: hgpio4-pins {
1066 groups = "hgpio4";
1067 function = "hgpio4";
1068 };
1069 hgpio5_pins: hgpio5-pins {
1070 groups = "hgpio5";
1071 function = "hgpio5";
1072 };
1073 hgpio6_pins: hgpio6-pins {
1074 groups = "hgpio6";
1075 function = "hgpio6";
1076 };
1077 hgpio7_pins: hgpio7-pins {
1078 groups = "hgpio7";
1079 function = "hgpio7";
1080 };
1081 jtag2_pins: jtag2-pins {
1082 groups = "jtag2";
1083 function = "jtag2";
1084 };
1085 };
Jim Liu147c0002022-09-27 16:45:15 +0800[diff] [blame]1086};