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git01.mediatek.com / filogic / uboot / dca22e5eda0d0148c42970b29d7f4019e9742cc3 / . / arch / arm / dts / imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi
blob: 9918f815343c420de17d965b326c65937cedd90a [file] [log] [blame]
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019 NXP
4 * Copyright (c) 2020 Amarula Solutons(India)
5 */
6
7#include "imx8mp-u-boot.dtsi"
8
9/ {
10 wdt-reboot {
11 compatible = "wdt-reboot";
12 wdt = <&wdog1>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]13 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]14 };
15
16 firmware {
17 optee {
18 compatible = "linaro,optee-tz";
19 method = "smc";
20 };
21 };
22};
23
24&reg_usdhc2_vmmc {
25 u-boot,off-on-delay-us = <20000>;
26};
27
28&reg_usdhc2_vmmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]29 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]30};
31
32&pinctrl_uart2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]33 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]34};
35
36&pinctrl_usdhc2_gpio {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]37 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]38};
39
40&pinctrl_usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]41 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]42};
43
44&pinctrl_usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]45 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]46};
47
48&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]49 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]50};
51
52&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]53 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]54};
55
56&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]57 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]58};
59
60&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]61 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]62};
63
64&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]65 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]66};
67
68&uart2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]69 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]70};
71
72&crypto {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]73 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]74};
75
76&sec_jr0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]77 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]78};
79
80&sec_jr1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]81 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]82};
83
84&sec_jr2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]85 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]86};
87
88&i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]89 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]90};
91
92&i2c2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]93 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]94};
95
96&i2c3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]97 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]98};
99
100&i2c4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]101 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]102};
103
104&i2c5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]105 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]106};
107
108&i2c6 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]109 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]110};
111
112&usdhc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]113 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]114};
115
116&usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]117 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]118 sd-uhs-sdr104;
119 sd-uhs-ddr50;
120 no-1-8-v;
121};
122
123&usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]124 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]125 mmc-hs400-1_8v;
126 mmc-hs400-enhanced-strobe;
127};
128
129&wdog1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]130 bootph-pre-ram;
Manoj Sai38b4c762022-08-26 18:03:37 +0530[diff] [blame]131};
132
133&eqos {
134 /delete-property/ assigned-clocks;
135 /delete-property/ assigned-clock-parents;
136 /delete-property/ assigned-clock-rates;
137};
138
139&ethphy0 {
140 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
141 reset-delay-us = <15000>;
142 reset-post-delay-us = <100000>;
143};
144
145&fec {
146 phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
147 phy-reset-duration = <15>;
148 phy-reset-post-delay = <100>;
149};