blob: 43b669c642cece4413f4b7f45fe8b5bc17463df8 [file] [log] [blame]
Mathew McBridee605fb12022-01-31 18:34:43 +05301// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree file for Travese Ten64 (LS1088) board
4 * Based on fsl-ls1088a-rdb.dts
5 * Copyright 2017-2020 NXP
6 * Copyright 2019-2021 Traverse Technologies
7 *
8 * Author: Mathew McBride <matt@traverse.com.au>
9 */
10
11/dts-v1/;
12
13#include "fsl-ls1088a.dtsi"
14
15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/input/input.h>
17
18/ {
19 model = "Traverse Ten64";
20 compatible = "traverse,ten64", "fsl,ls1088a";
21
22 aliases {
23 spi0 = &qspi;
24 };
25
26 chosen {
27 stdout-path = "serial0:115200n8";
28 };
29
30 buttons {
31 compatible = "gpio-keys";
32
33 /* Fired by system controller when
34 * external power off (e.g ATX Power Button)
35 * asserted
36 */
37 powerdn {
38 label = "External Power Down";
39 gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
40 interrupts = <&gpio1 17 IRQ_TYPE_EDGE_FALLING>;
41 linux,code = <KEY_POWER>;
42 };
43
44 /* Rear Panel 'ADMIN' button (GPIO_H) */
45 admin {
46 label = "ADMIN button";
47 gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>;
48 interrupts = <&gpio3 8 IRQ_TYPE_EDGE_RISING>;
49 linux,code = <KEY_WPS_BUTTON>;
50 };
51 };
52
53 leds {
54 compatible = "gpio-leds";
55
56 sfp1down {
57 label = "ten64:green:sfp1:down";
58 gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>;
59 };
60
61 sfp2up {
62 label = "ten64:green:sfp2:up";
63 gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
64 };
65
66 admin {
67 label = "ten64:admin";
68 gpios = <&sfpgpio 12 GPIO_ACTIVE_HIGH>;
69 };
70 };
71
72 sfp_xg0: dpmac2-sfp {
73 compatible = "sff,sfp";
74 i2c-bus = <&sfplower_i2c>;
75 tx-fault-gpios = <&sfpgpio 0 GPIO_ACTIVE_HIGH>;
76 tx-disable-gpios = <&sfpgpio 1 GPIO_ACTIVE_HIGH>;
77 mod-def0-gpios = <&sfpgpio 2 GPIO_ACTIVE_LOW>;
78 los-gpios = <&sfpgpio 3 GPIO_ACTIVE_HIGH>;
79 maximum-power-milliwatt = <2000>;
80 };
81
82 sfp_xg1: dpmac1-sfp {
83 compatible = "sff,sfp";
84 i2c-bus = <&sfpupper_i2c>;
85 tx-fault-gpios = <&sfpgpio 4 GPIO_ACTIVE_HIGH>;
86 tx-disable-gpios = <&sfpgpio 5 GPIO_ACTIVE_HIGH>;
87 mod-def0-gpios = <&sfpgpio 6 GPIO_ACTIVE_LOW>;
88 los-gpios = <&sfpgpio 7 GPIO_ACTIVE_HIGH>;
89 maximum-power-milliwatt = <2000>;
90 };
91};
92
93/* XG1 - Upper SFP */
94&dpmac1 {
95 sfp = <&sfp_xg1>;
96 phy-connection-type = "10gbase-r";
97 managed = "in-band-status";
98 status = "okay";
99};
100
101/* XG0 - Lower SFP */
102&dpmac2 {
103 sfp = <&sfp_xg0>;
104 phy-connection-type = "10gbase-r";
105 managed = "in-band-status";
106 status = "okay";
107};
108
109/* DPMAC3..6 is GE4 to GE8 */
110&dpmac3 {
111 phy-handle = <&mdio1_phy5>;
112 phy-connection-type = "qsgmii";
113 managed = "in-band-status";
114 status = "okay";
115};
116
117&dpmac4 {
118 phy-handle = <&mdio1_phy6>;
119 phy-connection-type = "qsgmii";
120 managed = "in-band-status";
121 status = "okay";
122};
123
124&dpmac5 {
125 phy-handle = <&mdio1_phy7>;
126 phy-connection-type = "qsgmii";
127 managed = "in-band-status";
128 status = "okay";
129};
130
131&dpmac6 {
132 phy-handle = <&mdio1_phy8>;
133 phy-connection-type = "qsgmii";
134 managed = "in-band-status";
135 status = "okay";
136};
137
138/* DPMAC7..10 is GE0 to GE3 */
139&dpmac7 {
140 phy-handle = <&mdio1_phy1>;
141 phy-connection-type = "qsgmii";
142 managed = "in-band-status";
143 status = "okay";
144};
145
146&dpmac8 {
147 phy-handle = <&mdio1_phy2>;
148 phy-connection-type = "qsgmii";
149 managed = "in-band-status";
150 status = "okay";
151};
152
153&dpmac9 {
154 phy-handle = <&mdio1_phy3>;
155 phy-connection-type = "qsgmii";
156 managed = "in-band-status";
157 status = "okay";
158};
159
160&dpmac10 {
161 phy-handle = <&mdio1_phy4>;
162 phy-connection-type = "qsgmii";
163 managed = "in-band-status";
164 status = "okay";
165};
166
167&serial0 {
168 status = "okay";
169};
170
171&serial1 {
172 status = "okay";
173};
174
175&emdio1 {
176 status = "okay";
177
178 mdio1_phy5: ethernet-phy@c {
179 reg = <0xc>;
180 };
181
182 mdio1_phy6: ethernet-phy@d {
183 reg = <0xd>;
184 };
185
186 mdio1_phy7: ethernet-phy@e {
187 reg = <0xe>;
188 };
189
190 mdio1_phy8: ethernet-phy@f {
191 reg = <0xf>;
192 };
193
194 mdio1_phy1: ethernet-phy@1c {
195 reg = <0x1c>;
196 };
197
198 mdio1_phy2: ethernet-phy@1d {
199 reg = <0x1d>;
200 };
201
202 mdio1_phy3: ethernet-phy@1e {
203 reg = <0x1e>;
204 };
205
206 mdio1_phy4: ethernet-phy@1f {
207 reg = <0x1f>;
208 };
209};
210
211&esdhc {
212 status = "okay";
213};
214
215&i2c0 {
216 status = "okay";
217
218 sfpgpio: gpio@76 {
219 compatible = "ti,tca9539";
220 reg = <0x76>;
221 #gpio-cells = <2>;
222 gpio-controller;
223
224 admin_led_lower {
225 gpio-hog;
226 gpios = <13 GPIO_ACTIVE_HIGH>;
227 output-low;
228 };
229 };
230
231 at97sc: tpm@29 {
232 compatible = "atmel,at97sc3204t";
233 reg = <0x29>;
234 };
235
236 uc: board-controller@7e {
237 compatible = "traverse,ten64-controller";
238 reg = <0x7e>;
239 };
240};
241
242&i2c2 {
243 status = "okay";
244
245 rx8035: rtc@32 {
246 compatible = "epson,rx8035";
247 reg = <0x32>;
248 };
249};
250
251&i2c3 {
252 status = "okay";
253
254 i2c-switch@70 {
255 compatible = "nxp,pca9540";
256 #address-cells = <1>;
257 #size-cells = <0>;
258 reg = <0x70>;
259
260 sfpupper_i2c: i2c@0 {
261 #address-cells = <1>;
262 #size-cells = <0>;
263 reg = <0>;
264 };
265
266 sfplower_i2c: i2c@1 {
267 #address-cells = <1>;
268 #size-cells = <0>;
269 reg = <1>;
270 };
271 };
272};
273
274&qspi {
275 status = "okay";
276
277 en25s64: flash@0 {
278 compatible = "jedec,spi-nor";
279 #address-cells = <1>;
280 #size-cells = <1>;
281 reg = <0>;
282 spi-max-frequency = <20000000>;
283 spi-rx-bus-width = <4>;
284 spi-tx-bus-width = <4>;
285
286 partitions {
287 compatible = "fixed-partitions";
288 #address-cells = <1>;
289 #size-cells = <1>;
290
291 partition@0 {
292 label = "bl2";
293 reg = <0 0x100000>;
294 };
295
296 partition@100000 {
297 label = "bl3";
298 reg = <0x100000 0x200000>;
299 };
300
301 partition@300000 {
302 label = "mcfirmware";
303 reg = <0x300000 0x200000>;
304 };
305
306 partition@500000 {
307 label = "ubootenv";
308 reg = <0x500000 0x80000>;
309 };
310
311 partition@580000 {
312 label = "dpl";
313 reg = <0x580000 0x40000>;
314 };
315
316 partition@5C0000 {
317 label = "dpc";
318 reg = <0x5C0000 0x40000>;
319 };
320
321 partition@600000 {
322 label = "devicetree";
323 reg = <0x600000 0x40000>;
324 };
325 };
326 };
327
328 nand: flash@1 {
329 compatible = "spi-nand";
330 #address-cells = <1>;
331 #size-cells = <1>;
332 reg = <1>;
333 spi-max-frequency = <20000000>;
334 spi-rx-bus-width = <4>;
335 spi-tx-bus-width = <4>;
336
337 partitions {
338 compatible = "fixed-partitions";
339 #address-cells = <1>;
340 #size-cells = <1>;
341
342 /* reserved for future boot direct from NAND flash
343 * (this would use the same layout as the 8MiB NOR flash)
344 */
345 partition@0 {
346 label = "nand-boot-reserved";
347 reg = <0 0x800000>;
348 };
349
350 /* recovery / install environment */
351 partition@800000 {
352 label = "recovery";
353 reg = <0x800000 0x2000000>;
354 };
355
356 /* ubia (first OpenWrt) - a/b names to prevent confusion with ubi0/1/etc. */
357 partition@2800000 {
358 label = "ubia";
359 reg = <0x2800000 0x6C00000>;
360 };
361
362 /* ubib (second OpenWrt) */
363 partition@9400000 {
364 label = "ubib";
365 reg = <0x9400000 0x6C00000>;
366 };
367 };
368 };
369};
370
371&usb0 {
372 status = "okay";
373};
374
375&usb1 {
376 status = "okay";
377};