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git01.mediatek.com / filogic / uboot / dc7769008fe5c90ead564dbb634f179f64c58a13 / . / configs / j721e_hs_evm_r5_defconfig
blob: 1e4a93ff53fea26034b13abda6a36babd7e871ad [file] [log] [blame]
Andrew F. Davis74ebb782020-01-10 14:35:23 -0500[diff] [blame]1CONFIG_ARM=y
2CONFIG_ARCH_K3=y
3CONFIG_TI_SECURE_DEVICE=y
Tom Rinie25a03a2021-11-01 12:19:22 +0000[diff] [blame]4CONFIG_SYS_MALLOC_LEN=0x2000000
5CONFIG_SYS_MALLOC_F_LEN=0x55000
Simon Glass035939e2021-07-10 21:14:30 -0600[diff] [blame]6CONFIG_SPL_GPIO=y
Andrew F. Davis74ebb782020-01-10 14:35:23 -0500[diff] [blame]7CONFIG_SPL_LIBCOMMON_SUPPORT=y
8CONFIG_SPL_LIBGENERIC_SUPPORT=y
Andrew F. Davis74ebb782020-01-10 14:35:23 -0500[diff] [blame]9CONFIG_SOC_K3_J721E=y
10CONFIG_TARGET_J721E_R5_EVM=y
11CONFIG_ENV_SIZE=0x20000
12CONFIG_ENV_OFFSET=0x680000
Tom Rinif6e6e1a2020-01-22 13:38:00 -0500[diff] [blame]13CONFIG_DM_GPIO=y
Tom Rini6c75e632020-06-16 19:06:29 -0400[diff] [blame]14CONFIG_SPL_DM_SPI=y
Tom Rinia20e51f2021-06-28 10:17:29 -0400[diff] [blame]15CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-r5-common-proc-board"
Tom Rini0332a1a2020-07-06 13:54:25 -0400[diff] [blame]16CONFIG_SPL_TEXT_BASE=0x41c00000
Simon Glassb58bfe02021-08-08 12:20:09 -0600[diff] [blame]17CONFIG_SPL_MMC=y
Simon Glassf4d60392021-08-08 12:20:12 -0600[diff] [blame]18CONFIG_SPL_SERIAL=y
Simon Glass284cb9c2021-07-10 21:14:31 -0600[diff] [blame]19CONFIG_SPL_DRIVERS_MISC=y
Andrew F. Davis74ebb782020-01-10 14:35:23 -0500[diff] [blame]20CONFIG_SPL_STACK_R_ADDR=0x82000000
Tom Rinid49f5822020-02-28 13:28:38 -0500[diff] [blame]21CONFIG_ENV_OFFSET_REDUND=0x700000
Andrew F. Davis74ebb782020-01-10 14:35:23 -0500[diff] [blame]22CONFIG_SPL_FS_FAT=y
23CONFIG_SPL_LIBDISK_SUPPORT=y
24CONFIG_SPL_SPI_FLASH_SUPPORT=y
Simon Glassa5820472021-08-08 12:20:14 -0600[diff] [blame]25CONFIG_SPL_SPI=y
Andrew F. Davis74ebb782020-01-10 14:35:23 -0500[diff] [blame]26# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
27CONFIG_SPL_LOAD_FIT=y
Peng Fan54590592020-07-06 15:35:01 +0800[diff] [blame]28CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
Andrew F. Davis74ebb782020-01-10 14:35:23 -0500[diff] [blame]29CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
Simon Glass5d144112020-07-19 13:56:10 -0600[diff] [blame]30# CONFIG_USE_SPL_FIT_GENERATOR is not set
Andrew F. Davis74ebb782020-01-10 14:35:23 -0500[diff] [blame]31CONFIG_USE_BOOTCOMMAND=y
32# CONFIG_DISPLAY_CPUINFO is not set
33CONFIG_SPL_STACK_R=y
34CONFIG_SPL_SEPARATE_BSS=y
35CONFIG_SPL_EARLY_BSS=y
Vignesh Raghavendra88c08222020-02-04 11:09:59 +0530[diff] [blame]36CONFIG_SPL_DMA=y
Andrew F. Davis74ebb782020-01-10 14:35:23 -0500[diff] [blame]37CONFIG_SPL_ENV_SUPPORT=y
Simon Glassbccfc2e2021-07-10 21:14:36 -0600[diff] [blame]38CONFIG_SPL_I2C=y
Andrew F. Davis74ebb782020-01-10 14:35:23 -0500[diff] [blame]39CONFIG_SPL_DM_MAILBOX=y
Lukasz Majewski76f442982020-06-04 23:11:53 +0800[diff] [blame]40CONFIG_SPL_DM_SPI_FLASH=y
Andrew F. Davis74ebb782020-01-10 14:35:23 -0500[diff] [blame]41CONFIG_SPL_DM_RESET=y
Andrew F. Davis74ebb782020-01-10 14:35:23 -0500[diff] [blame]42CONFIG_SPL_POWER_DOMAIN=y
43CONFIG_SPL_RAM_SUPPORT=y
44CONFIG_SPL_RAM_DEVICE=y
45CONFIG_SPL_REMOTEPROC=y
Vignesh Raghavendra88c08222020-02-04 11:09:59 +0530[diff] [blame]46# CONFIG_SPL_SPI_FLASH_TINY is not set
47CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
Andrew F. Davis74ebb782020-01-10 14:35:23 -0500[diff] [blame]48CONFIG_SPL_SPI_LOAD=y
Tom Rinie22fa4f2021-08-10 15:08:46 -0400[diff] [blame]49CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
Andrew F. Davis74ebb782020-01-10 14:35:23 -0500[diff] [blame]50CONFIG_SPL_YMODEM_SUPPORT=y
51CONFIG_HUSH_PARSER=y
52# CONFIG_CMD_FLASH is not set
53CONFIG_CMD_GPT=y
54CONFIG_CMD_MMC=y
55CONFIG_CMD_REMOTEPROC=y
56# CONFIG_CMD_SETEXPR is not set
57CONFIG_CMD_TIME=y
58CONFIG_CMD_FAT=y
59CONFIG_OF_CONTROL=y
60CONFIG_SPL_OF_CONTROL=y
Adam Ford710966e2020-07-03 06:48:56 -0500[diff] [blame]61CONFIG_ENV_OVERWRITE=y
Andrew F. Davis74ebb782020-01-10 14:35:23 -0500[diff] [blame]62CONFIG_ENV_IS_IN_MMC=y
63CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
Andrew F. Davis74ebb782020-01-10 14:35:23 -0500[diff] [blame]64CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Tom Rinieb1f9092020-07-24 17:14:47 -0400[diff] [blame]65CONFIG_SYS_MMC_ENV_PART=1
Andrew F. Davis74ebb782020-01-10 14:35:23 -0500[diff] [blame]66CONFIG_DM=y
67CONFIG_SPL_DM=y
68CONFIG_SPL_DM_SEQ_ALIAS=y
69CONFIG_REGMAP=y
70CONFIG_SPL_REGMAP=y
71CONFIG_SPL_OF_TRANSLATE=y
72CONFIG_CLK=y
73CONFIG_SPL_CLK=y
74CONFIG_CLK_TI_SCI=y
Vignesh Raghavendra88c08222020-02-04 11:09:59 +0530[diff] [blame]75CONFIG_DMA_CHANNELS=y
76CONFIG_TI_K3_NAVSS_UDMA=y
Andrew F. Davis74ebb782020-01-10 14:35:23 -0500[diff] [blame]77CONFIG_TI_SCI_PROTOCOL=y
Andrew F. Davis74ebb782020-01-10 14:35:23 -0500[diff] [blame]78CONFIG_DA8XX_GPIO=y
79CONFIG_DM_I2C=y
80CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
81CONFIG_SYS_I2C_OMAP24XX=y
82CONFIG_DM_MAILBOX=y
83CONFIG_K3_SEC_PROXY=y
Andrew F. Davis74ebb782020-01-10 14:35:23 -0500[diff] [blame]84CONFIG_FS_LOADER=y
Keerthyfe8f6092022-01-27 13:16:53 +0100[diff] [blame]85CONFIG_SPL_FS_LOADER=y
Andrew F. Davis74ebb782020-01-10 14:35:23 -0500[diff] [blame]86CONFIG_K3_AVS0=y
Andrew F. Davis74ebb782020-01-10 14:35:23 -0500[diff] [blame]87CONFIG_MMC_SDHCI=y
88CONFIG_SPL_MMC_SDHCI_ADMA=y
89CONFIG_MMC_SDHCI_AM654=y
90CONFIG_MTD=y
91CONFIG_DM_SPI_FLASH=y
Vignesh Raghavendra88c08222020-02-04 11:09:59 +0530[diff] [blame]92CONFIG_SPI_FLASH_SFDP_SUPPORT=y
Andrew F. Davis74ebb782020-01-10 14:35:23 -0500[diff] [blame]93CONFIG_SPI_FLASH_STMICRO=y
94CONFIG_PINCTRL=y
95# CONFIG_PINCTRL_GENERIC is not set
96CONFIG_SPL_PINCTRL=y
97# CONFIG_SPL_PINCTRL_GENERIC is not set
98CONFIG_PINCTRL_SINGLE=y
99CONFIG_POWER_DOMAIN=y
100CONFIG_TI_SCI_POWER_DOMAIN=y
101CONFIG_DM_PMIC=y
102CONFIG_PMIC_TPS65941=y
103CONFIG_DM_REGULATOR=y
104CONFIG_SPL_DM_REGULATOR=y
105CONFIG_DM_REGULATOR_TPS65941=y
106CONFIG_K3_SYSTEM_CONTROLLER=y
107CONFIG_REMOTEPROC_TI_K3_ARM64=y
108CONFIG_DM_RESET=y
109CONFIG_RESET_TI_SCI=y
110CONFIG_DM_SERIAL=y
Tom Rini84610272020-07-28 08:46:52 -0400[diff] [blame]111CONFIG_SOC_DEVICE=y
112CONFIG_SOC_DEVICE_TI_K3=y
Vignesh Raghavendra88c08222020-02-04 11:09:59 +0530[diff] [blame]113CONFIG_SOC_TI=y
Andrew F. Davis74ebb782020-01-10 14:35:23 -0500[diff] [blame]114CONFIG_SPI=y
115CONFIG_DM_SPI=y
116CONFIG_CADENCE_QSPI=y
117CONFIG_SYSRESET=y
118CONFIG_SPL_SYSRESET=y
119CONFIG_SYSRESET_TI_SCI=y
120CONFIG_TIMER=y
121CONFIG_SPL_TIMER=y
122CONFIG_OMAP_TIMER=y
123CONFIG_FS_EXT4=y
124CONFIG_FS_FAT_MAX_CLUSTSIZE=16384