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wdenk4e112c12003-06-03 23:54:09 +00001/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include "mpc8xx.h"
26#include <linux/mtd/doc2000.h>
27
28extern int kbd_init(void);
29extern int drv_kbd_init(void);
30
31/* ------------------------------------------------------------------------- */
32
33static long int dram_size (long int, long int *, long int);
34
35/* ------------------------------------------------------------------------- */
36
37#define _NOT_USED_ 0xFFFFFFFF
38
39const uint sdram_table[] =
40{
41 /*
42 * Single Read. (Offset 0 in UPMA RAM)
43 */
44 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
45 0x1FF77C47, /* last */
46 /*
47 * SDRAM Initialization (offset 5 in UPMA RAM)
48 *
49 * This is no UPM entry point. The following definition uses
50 * the remaining space to establish an initialization
51 * sequence, which is executed by a RUN command.
52 *
53 */
54 0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */
55 /*
56 * Burst Read. (Offset 8 in UPMA RAM)
57 */
58 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
59 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
60 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
61 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
62 /*
63 * Single Write. (Offset 18 in UPMA RAM)
64 */
65 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
66 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
67 /*
68 * Burst Write. (Offset 20 in UPMA RAM)
69 */
70 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
71 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
72 _NOT_USED_,
73 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
74 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
75 /*
76 * Refresh (Offset 30 in UPMA RAM)
77 */
78 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
79 0xFFFFFC84, 0xFFFFFC07, /* last */
80 _NOT_USED_, _NOT_USED_,
81 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
82 /*
83 * Exception. (Offset 3c in UPMA RAM)
84 */
85 0x1FF7FC07, /* last */
86 _NOT_USED_, _NOT_USED_, _NOT_USED_,
87};
88
89const uint static_table[] =
90{
91 /*
92 * Single Read. (Offset 0 in UPMA RAM)
93 */
94 0x0FFFFC04, 0x0FF3FC04, 0x0FF3CC04, 0x0FF3CC04,
95 0x0FF3EC04, 0x0FF3CC00, 0x0FF7FC04, 0x3FFFFC04,
96 0xFFFFFC04, 0xFFFFFC05, /* last */
97 _NOT_USED_, _NOT_USED_,
98 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
99 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
100 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
101 /*
102 * Single Write. (Offset 18 in UPMA RAM)
103 */
104 0x0FFFFC04, 0x00FFFC04, 0x00FFFC04, 0x00FFFC04,
105 0x01FFFC00, 0x3FFFFC04, 0xFFFFFC04, 0xFFFFFC05, /* last */
106 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
107 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
108 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
109 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
110 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
111 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
112 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
113 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
114};
115
116/* ------------------------------------------------------------------------- */
117
118/*
119 * Check Board Identity:
120 *
121 * Test TQ ID string (TQM8xx...)
122 * If present, check for "L" type (no second DRAM bank),
123 * otherwise "L" type is assumed as default.
124 *
125 * Return 1 for "L" type, 0 else.
126 */
127
128int checkboard (void)
129{
Wolfgang Denk7fb52662005-10-13 16:45:02 +0200130 char *s = getenv ("serial#");
wdenk4e112c12003-06-03 23:54:09 +0000131
wdenk87249ba2004-01-06 22:38:14 +0000132 if (!s || strncmp (s, "TQM8", 4)) {
133 printf ("### No HW ID - assuming RBC823\n");
134 return (0);
135 }
wdenk4e112c12003-06-03 23:54:09 +0000136
wdenk87249ba2004-01-06 22:38:14 +0000137 puts (s);
138 putc ('\n');
wdenk4e112c12003-06-03 23:54:09 +0000139
wdenk87249ba2004-01-06 22:38:14 +0000140 return (0);
wdenk4e112c12003-06-03 23:54:09 +0000141}
142
143/* ------------------------------------------------------------------------- */
144
Becky Brucebd99ae72008-06-09 16:03:40 -0500145phys_size_t initdram (int board_type)
wdenk4e112c12003-06-03 23:54:09 +0000146{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200147 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenk87249ba2004-01-06 22:38:14 +0000148 volatile memctl8xx_t *memctl = &immap->im_memctl;
149 long int size_b0, size8, size9;
wdenk4e112c12003-06-03 23:54:09 +0000150
wdenk87249ba2004-01-06 22:38:14 +0000151 upmconfig (UPMA, (uint *) sdram_table,
152 sizeof (sdram_table) / sizeof (uint));
wdenk4e112c12003-06-03 23:54:09 +0000153
wdenk87249ba2004-01-06 22:38:14 +0000154 /*
155 * 1 Bank of 64Mbit x 2 devices
156 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200157 memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_4K;
wdenk87249ba2004-01-06 22:38:14 +0000158 memctl->memc_mar = 0x00000088;
wdenk4e112c12003-06-03 23:54:09 +0000159
wdenk87249ba2004-01-06 22:38:14 +0000160 /*
161 * Map controller SDRAM bank 0
162 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200163 memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
164 memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
165 memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
wdenk87249ba2004-01-06 22:38:14 +0000166 udelay (200);
wdenk4e112c12003-06-03 23:54:09 +0000167
wdenk87249ba2004-01-06 22:38:14 +0000168 /*
169 * Perform SDRAM initializsation sequence
170 */
171 memctl->memc_mcr = 0x80008105; /* SDRAM bank 0 */
172 udelay (1);
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200173 memctl->memc_mamr = (CONFIG_SYS_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_8X;
wdenk87249ba2004-01-06 22:38:14 +0000174 udelay (200);
175 memctl->memc_mcr = 0x80008130; /* SDRAM bank 0 - execute twice */
176 udelay (1);
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200177 memctl->memc_mamr = (CONFIG_SYS_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_4X;
wdenk87249ba2004-01-06 22:38:14 +0000178 udelay (200);
wdenk4e112c12003-06-03 23:54:09 +0000179
wdenk87249ba2004-01-06 22:38:14 +0000180 memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
181 udelay (1000);
wdenk4e112c12003-06-03 23:54:09 +0000182
wdenk87249ba2004-01-06 22:38:14 +0000183 /*
184 * Preliminary prescaler for refresh (depends on number of
185 * banks): This value is selected for four cycles every 62.4 us
186 * with two SDRAM banks or four cycles every 31.2 us with one
187 * bank. It will be adjusted after memory sizing.
188 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200189 memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; /* 16: but should be: CONFIG_SYS_MPTPR_1BK_4K */
wdenk4e112c12003-06-03 23:54:09 +0000190
wdenk87249ba2004-01-06 22:38:14 +0000191 /*
192 * Check Bank 0 Memory Size for re-configuration
193 *
194 * try 8 column mode
195 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200196 size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE4_PRELIM,
wdenk87249ba2004-01-06 22:38:14 +0000197 SDRAM_MAX_SIZE);
198 udelay (1000);
wdenk4e112c12003-06-03 23:54:09 +0000199
wdenk87249ba2004-01-06 22:38:14 +0000200 /*
201 * try 9 column mode
202 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200203 size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE4_PRELIM,
wdenk87249ba2004-01-06 22:38:14 +0000204 SDRAM_MAX_SIZE);
wdenk4e112c12003-06-03 23:54:09 +0000205
wdenk87249ba2004-01-06 22:38:14 +0000206 if (size8 < size9) { /* leave configuration at 9 columns */
207 size_b0 = size9;
wdenk4e112c12003-06-03 23:54:09 +0000208/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
wdenk87249ba2004-01-06 22:38:14 +0000209 } else { /* back to 8 columns */
210 size_b0 = size8;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200211 memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
wdenk87249ba2004-01-06 22:38:14 +0000212 udelay (500);
wdenk4e112c12003-06-03 23:54:09 +0000213/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
wdenk87249ba2004-01-06 22:38:14 +0000214 }
wdenk4e112c12003-06-03 23:54:09 +0000215
wdenk87249ba2004-01-06 22:38:14 +0000216 udelay (1000);
wdenk4e112c12003-06-03 23:54:09 +0000217
wdenk87249ba2004-01-06 22:38:14 +0000218 /*
219 * Adjust refresh rate depending on SDRAM type, both banks
220 * For types > 128 MBit leave it at the current (fast) rate
221 */
222 if ((size_b0 < 0x02000000)) {
223 /* reduce to 15.6 us (62.4 us / quad) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200224 memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
wdenk87249ba2004-01-06 22:38:14 +0000225 udelay (1000);
226 }
wdenk4e112c12003-06-03 23:54:09 +0000227
wdenk87249ba2004-01-06 22:38:14 +0000228 /* SDRAM Bank 0 is bigger - map first */
wdenk4e112c12003-06-03 23:54:09 +0000229
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200230 memctl->memc_or4 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
231 memctl->memc_br4 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
wdenk4e112c12003-06-03 23:54:09 +0000232
wdenk87249ba2004-01-06 22:38:14 +0000233 udelay (10000);
wdenk4e112c12003-06-03 23:54:09 +0000234
wdenk87249ba2004-01-06 22:38:14 +0000235 return (size_b0);
wdenk4e112c12003-06-03 23:54:09 +0000236}
237
238/* ------------------------------------------------------------------------- */
239
240/*
241 * Check memory range for valid RAM. A simple memory test determines
242 * the actually available RAM size between addresses `base' and
243 * `base + maxsize'. Some (not all) hardware errors are detected:
244 * - short between address lines
245 * - short between data lines
246 */
247
wdenk87249ba2004-01-06 22:38:14 +0000248static long int dram_size (long int mamr_value, long int *base,
249 long int maxsize)
wdenk4e112c12003-06-03 23:54:09 +0000250{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200251 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenk87249ba2004-01-06 22:38:14 +0000252 volatile memctl8xx_t *memctl = &immap->im_memctl;
wdenk4e112c12003-06-03 23:54:09 +0000253
wdenk87249ba2004-01-06 22:38:14 +0000254 memctl->memc_mamr = mamr_value;
wdenk4e112c12003-06-03 23:54:09 +0000255
wdenk87249ba2004-01-06 22:38:14 +0000256 return (get_ram_size (base, maxsize));
wdenk4e112c12003-06-03 23:54:09 +0000257}
258
Wolfgang Denk21a51f02009-07-19 19:37:24 +0200259#ifdef CONFIG_CMD_DOC
wdenk87249ba2004-01-06 22:38:14 +0000260void doc_init (void)
wdenk4e112c12003-06-03 23:54:09 +0000261{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200262 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenk87249ba2004-01-06 22:38:14 +0000263 volatile memctl8xx_t *memctl = &immap->im_memctl;
wdenk4e112c12003-06-03 23:54:09 +0000264
wdenk87249ba2004-01-06 22:38:14 +0000265 upmconfig (UPMB, (uint *) static_table,
266 sizeof (static_table) / sizeof (uint));
267 memctl->memc_mbmr = MAMR_DSA_1_CYCL;
wdenk4e112c12003-06-03 23:54:09 +0000268
wdenk87249ba2004-01-06 22:38:14 +0000269 doc_probe (FLASH_BASE1_PRELIM);
wdenk4e112c12003-06-03 23:54:09 +0000270}
Wolfgang Denk21a51f02009-07-19 19:37:24 +0200271#endif