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wdenkd9fd6ff2002-10-11 08:43:32 +00001/*
2 * (C) Copyright 2002
3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
4 *
5 * (C) Copyright 2002
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <asm/arch/pxa-regs.h>
29#include <common.h>
Ben Warren0fd6aae2009-10-04 22:37:03 -070030#include <netdev.h>
Marek Vasut2db1e962010-09-09 09:50:39 +020031#include <asm/io.h>
wdenkd9fd6ff2002-10-11 08:43:32 +000032
Wolfgang Denk6405a152006-03-31 18:32:53 +020033DECLARE_GLOBAL_DATA_PTR;
34
wdenkd9fd6ff2002-10-11 08:43:32 +000035/* ------------------------------------------------------------------------- */
36
37
38/* local prototypes */
39void set_led (int led, int color);
40void error_code_halt (int code);
41int init_sio (int led, unsigned long base);
42inline void cradle_outb (unsigned short val, unsigned long base,
43 unsigned long reg);
44inline unsigned char cradle_inb (unsigned long base, unsigned long reg);
45inline void sleep (int i);
46
47inline void
48/**********************************************************/
49sleep (int i)
50/**********************************************************/
51{
52 while (i--) {
53 udelay (1000000);
54 }
55}
56
57void
58/**********************************************************/
59error_code_halt (int code)
60/**********************************************************/
61{
62 while (1) {
63 led_code (code, RED);
64 sleep (1);
65 led_code (0, OFF);
66 sleep (1);
67 }
68}
69
70void
71/**********************************************************/
72led_code (int code, int color)
73/**********************************************************/
74{
75 int i;
76
77 code &= 0xf; /* only 4 leds */
78
79 for (i = 0; i < 4; i++) {
80 if (code & (1 << i)) {
81 set_led (i, color);
82 } else {
83 set_led (i, OFF);
84 }
85 }
86}
87
88void
89/**********************************************************/
90set_led (int led, int color)
91/**********************************************************/
92{
93 int shift = led * 2;
94 unsigned long mask = 0x3 << shift;
95
Marek Vasut2db1e962010-09-09 09:50:39 +020096 writel(mask, GPCR2); /* clear bits */
97 writel((color << shift), GPSR2); /* set bits */
wdenkd9fd6ff2002-10-11 08:43:32 +000098 udelay (5000);
99}
100
101inline void
102/**********************************************************/
103cradle_outb (unsigned short val, unsigned long base, unsigned long reg)
104/**********************************************************/
105{
106 *(volatile unsigned short *) (base + (reg * 2)) = val;
107}
108
109inline unsigned char
110/**********************************************************/
111cradle_inb (unsigned long base, unsigned long reg)
112/**********************************************************/
113{
114 unsigned short val;
115
116 val = *(volatile unsigned short *) (base + (reg * 2));
117 return (val & 0xff);
118}
119
120int
121/**********************************************************/
122init_sio (int led, unsigned long base)
123/**********************************************************/
124{
125 unsigned char val;
126
127 set_led (led, YELLOW);
128 val = cradle_inb (base, CRADLE_SIO_INDEX);
129 val = cradle_inb (base, CRADLE_SIO_INDEX);
130 if (val != 0) {
131 set_led (led, RED);
132 return -1;
133 }
134
135 /* map SCC2 to COM1 */
136 cradle_outb (0x01, base, CRADLE_SIO_INDEX);
137 cradle_outb (0x00, base, CRADLE_SIO_DATA);
138
139 /* enable SCC2 extended regs */
140 cradle_outb (0x40, base, CRADLE_SIO_INDEX);
141 cradle_outb (0xa0, base, CRADLE_SIO_DATA);
142
143 /* enable SCC2 clock multiplier */
144 cradle_outb (0x51, base, CRADLE_SIO_INDEX);
145 cradle_outb (0x04, base, CRADLE_SIO_DATA);
146
147 /* enable SCC2 */
148 cradle_outb (0x00, base, CRADLE_SIO_INDEX);
149 cradle_outb (0x04, base, CRADLE_SIO_DATA);
150
151 /* map SCC2 DMA to channel 0 */
152 cradle_outb (0x4f, base, CRADLE_SIO_INDEX);
153 cradle_outb (0x09, base, CRADLE_SIO_DATA);
154
155 /* read ID from SIO to check operation */
156 cradle_outb (0xe4, base, 0x3f8 + 0x3);
157 val = cradle_inb (base, 0x3f8 + 0x0);
158 if ((val & 0xf0) != 0x20) {
159 set_led (led, RED);
160 /* disable SCC2 */
161 cradle_outb (0, base, CRADLE_SIO_INDEX);
162 cradle_outb (0, base, CRADLE_SIO_DATA);
163 return -1;
164 }
165 /* set back to bank 0 */
166 cradle_outb (0, base, 0x3f8 + 0x3);
167 set_led (led, GREEN);
168 return 0;
169}
170
171/*
172 * Miscelaneous platform dependent initialisations
173 */
174
175int
176/**********************************************************/
wdenkda55c6e2004-01-20 23:12:12 +0000177board_late_init (void)
wdenkd9fd6ff2002-10-11 08:43:32 +0000178/**********************************************************/
179{
180 return (0);
181}
182
183int
184/**********************************************************/
185board_init (void)
186/**********************************************************/
187{
Marek Vasut52a3ed82010-10-20 20:17:51 +0200188 /* We have RAM, disable cache */
189 dcache_disable();
190 icache_disable();
191
wdenkd9fd6ff2002-10-11 08:43:32 +0000192 led_code (0xf, YELLOW);
193
194 /* arch number of HHP Cradle */
wdenk767fbd42004-10-10 18:41:04 +0000195 gd->bd->bi_arch_number = MACH_TYPE_HHP_CRADLE;
wdenkd9fd6ff2002-10-11 08:43:32 +0000196
197 /* adress of boot parameters */
198 gd->bd->bi_boot_params = 0xa0000100;
199
200 /* Init SIOs to enable SCC2 */
201 udelay (100000); /* delay makes it look neat */
202 init_sio (0, CRADLE_SIO1_PHYS);
203 udelay (100000);
204 init_sio (1, CRADLE_SIO2_PHYS);
205 udelay (100000);
206 init_sio (2, CRADLE_SIO3_PHYS);
207 udelay (100000);
208 set_led (3, GREEN);
209
210 return 1;
211}
212
Marek Vasut52a3ed82010-10-20 20:17:51 +0200213extern void pxa_dram_init(void);
214int dram_init(void)
wdenkd9fd6ff2002-10-11 08:43:32 +0000215{
Marek Vasut52a3ed82010-10-20 20:17:51 +0200216 pxa_dram_init();
217 gd->ram_size = PHYS_SDRAM_1_SIZE;
218 return 0;
219}
wdenkd9fd6ff2002-10-11 08:43:32 +0000220
Marek Vasut52a3ed82010-10-20 20:17:51 +0200221void dram_init_banksize(void)
222{
223 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
224 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
wdenkd9fd6ff2002-10-11 08:43:32 +0000225}
Ben Warren0fd6aae2009-10-04 22:37:03 -0700226
227#ifdef CONFIG_CMD_NET
228int board_eth_init(bd_t *bis)
229{
230 int rc = 0;
231#ifdef CONFIG_SMC91111
232 rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
233#endif
234 return rc;
235}
236#endif