Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2008 |
| 3 | * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. |
| 4 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 6 | */ |
| 7 | |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 8 | #include <common.h> |
| 9 | #include <asm/processor.h> |
| 10 | #include <asm/immap_85xx.h> |
Kumar Gala | 01135a8 | 2008-08-26 22:56:56 -0500 | [diff] [blame] | 11 | #include <asm/fsl_ddr_sdram.h> |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 12 | #include <asm/processor.h> |
| 13 | #include <asm/mmu.h> |
| 14 | #include <spd_sdram.h> |
| 15 | |
| 16 | |
| 17 | #if !defined(CONFIG_SPD_EEPROM) |
| 18 | /* |
| 19 | * Autodetect onboard DDR SDRAM on 85xx platforms |
| 20 | * |
| 21 | * NOTE: Some of the hardcoded values are hardware dependant, |
| 22 | * so this should be extended for other future boards |
| 23 | * using this routine! |
| 24 | */ |
Becky Bruce | 5e35d8a | 2010-12-17 17:17:56 -0600 | [diff] [blame] | 25 | phys_size_t fixed_sdram(void) |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 26 | { |
Andy Fleming | 992562c | 2012-10-23 19:03:46 -0500 | [diff] [blame] | 27 | volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR); |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 28 | |
| 29 | /* |
| 30 | * Disable memory controller. |
| 31 | */ |
| 32 | ddr->cs0_config = 0; |
| 33 | ddr->sdram_cfg = 0; |
| 34 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 35 | ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; |
| 36 | ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; |
| 37 | ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; |
| 38 | ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; |
| 39 | ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; |
| 40 | ddr->sdram_mode = CONFIG_SYS_DDR_MODE; |
| 41 | ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; |
| 42 | ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONFIG_2; |
| 43 | ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CONTROL; |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 44 | |
| 45 | asm ("sync;isync;msync"); |
| 46 | udelay(1000); |
| 47 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 48 | ddr->sdram_cfg = CONFIG_SYS_DDR_CONFIG; |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 49 | asm ("sync; isync; msync"); |
| 50 | udelay(1000); |
| 51 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 52 | if (get_ram_size(0, CONFIG_SYS_SDRAM_SIZE<<20) == CONFIG_SYS_SDRAM_SIZE<<20) { |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 53 | /* |
| 54 | * OK, size detected -> all done |
| 55 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 56 | return CONFIG_SYS_SDRAM_SIZE<<20; |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 57 | } |
| 58 | |
| 59 | return 0; /* nothing found ! */ |
| 60 | } |
| 61 | #endif |
| 62 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 63 | #if defined(CONFIG_SYS_DRAM_TEST) |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 64 | int testdram (void) |
| 65 | { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 66 | uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; |
| 67 | uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 68 | uint *p; |
| 69 | |
| 70 | printf ("SDRAM test phase 1:\n"); |
| 71 | for (p = pstart; p < pend; p++) |
| 72 | *p = 0xaaaaaaaa; |
| 73 | |
| 74 | for (p = pstart; p < pend; p++) { |
| 75 | if (*p != 0xaaaaaaaa) { |
| 76 | printf ("SDRAM test fails at: %08x\n", (uint) p); |
| 77 | return 1; |
| 78 | } |
| 79 | } |
| 80 | |
| 81 | printf ("SDRAM test phase 2:\n"); |
| 82 | for (p = pstart; p < pend; p++) |
| 83 | *p = 0x55555555; |
| 84 | |
| 85 | for (p = pstart; p < pend; p++) { |
| 86 | if (*p != 0x55555555) { |
| 87 | printf ("SDRAM test fails at: %08x\n", (uint) p); |
| 88 | return 1; |
| 89 | } |
| 90 | } |
| 91 | |
| 92 | printf ("SDRAM test passed.\n"); |
| 93 | return 0; |
| 94 | } |
| 95 | #endif |