stroese | de46bb6 | 2003-09-12 08:41:24 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2001-2003 |
| 3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #include <common.h> |
| 25 | #include <asm/processor.h> |
Matthias Fuchs | 5dde4e2 | 2009-02-20 10:19:19 +0100 | [diff] [blame] | 26 | #include <asm/io.h> |
stroese | de46bb6 | 2003-09-12 08:41:24 +0000 | [diff] [blame] | 27 | #include <command.h> |
| 28 | #include <malloc.h> |
| 29 | |
Wolfgang Denk | 6405a15 | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 30 | DECLARE_GLOBAL_DATA_PTR; |
stroese | de46bb6 | 2003-09-12 08:41:24 +0000 | [diff] [blame] | 31 | |
| 32 | /* fpga configuration data - not compressed, generated by bin2c */ |
| 33 | const unsigned char fpgadata[] = |
| 34 | { |
| 35 | #include "fpgadata.c" |
| 36 | }; |
| 37 | int filesize = sizeof(fpgadata); |
| 38 | |
| 39 | |
wdenk | da55c6e | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 40 | int board_early_init_f (void) |
stroese | de46bb6 | 2003-09-12 08:41:24 +0000 | [diff] [blame] | 41 | { |
| 42 | /* |
| 43 | * IRQ 0-15 405GP internally generated; active high; level sensitive |
| 44 | * IRQ 16 405GP internally generated; active low; level sensitive |
| 45 | * IRQ 17-24 RESERVED |
| 46 | * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive |
| 47 | * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive |
| 48 | * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive |
| 49 | * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive |
| 50 | * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive |
| 51 | * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive |
| 52 | * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive |
| 53 | */ |
| 54 | mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ |
| 55 | mtdcr(uicer, 0x00000000); /* disable all ints */ |
| 56 | mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ |
| 57 | mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */ |
| 58 | mtdcr(uictr, 0x10000000); /* set int trigger levels */ |
| 59 | mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ |
| 60 | mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ |
| 61 | |
| 62 | /* |
| 63 | * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us |
| 64 | */ |
| 65 | mtebc (epcr, 0xa8400000); /* ebc always driven */ |
| 66 | |
stroese | 4d34bbf | 2004-12-16 18:35:58 +0000 | [diff] [blame] | 67 | /* |
| 68 | * Reset CPLD via GPIO13 (CS4) pin |
| 69 | */ |
Matthias Fuchs | 5dde4e2 | 2009-02-20 10:19:19 +0100 | [diff] [blame] | 70 | out_be32((void *)GPIO0_OR, |
| 71 | in_be32((void *)GPIO0_OR) & ~(0x80000000 >> 13)); |
stroese | 4d34bbf | 2004-12-16 18:35:58 +0000 | [diff] [blame] | 72 | udelay(1000); /* wait 1ms */ |
Matthias Fuchs | 5dde4e2 | 2009-02-20 10:19:19 +0100 | [diff] [blame] | 73 | out_be32((void *)GPIO0_OR, |
| 74 | in_be32((void *)GPIO0_OR) | (0x80000000 >> 13)); |
stroese | 4d34bbf | 2004-12-16 18:35:58 +0000 | [diff] [blame] | 75 | udelay(1000); /* wait 1ms */ |
| 76 | |
stroese | de46bb6 | 2003-09-12 08:41:24 +0000 | [diff] [blame] | 77 | return 0; |
| 78 | } |
| 79 | |
stroese | de46bb6 | 2003-09-12 08:41:24 +0000 | [diff] [blame] | 80 | int misc_init_r (void) |
| 81 | { |
stroese | 4d34bbf | 2004-12-16 18:35:58 +0000 | [diff] [blame] | 82 | /* adjust flash start and offset */ |
| 83 | gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; |
| 84 | gd->bd->bi_flashoffset = 0; |
stroese | de46bb6 | 2003-09-12 08:41:24 +0000 | [diff] [blame] | 85 | |
| 86 | return (0); |
| 87 | } |
| 88 | |
| 89 | |
| 90 | /* |
| 91 | * Check Board Identity: |
| 92 | */ |
| 93 | |
| 94 | int checkboard (void) |
| 95 | { |
Wolfgang Denk | 7fb5266 | 2005-10-13 16:45:02 +0200 | [diff] [blame] | 96 | char str[64]; |
stroese | de46bb6 | 2003-09-12 08:41:24 +0000 | [diff] [blame] | 97 | int i = getenv_r ("serial#", str, sizeof(str)); |
| 98 | unsigned char trans[16] = {0x0,0x8,0x4,0xc,0x2,0xa,0x6,0xe, |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 99 | 0x1,0x9,0x5,0xd,0x3,0xb,0x7,0xf}; |
stroese | de46bb6 | 2003-09-12 08:41:24 +0000 | [diff] [blame] | 100 | unsigned char id1, id2; |
| 101 | |
| 102 | puts ("Board: "); |
| 103 | |
| 104 | if (i == -1) { |
| 105 | puts ("### No HW ID - assuming DP405"); |
| 106 | } else { |
| 107 | puts(str); |
| 108 | } |
| 109 | |
Matthias Fuchs | 5dde4e2 | 2009-02-20 10:19:19 +0100 | [diff] [blame] | 110 | id1 = trans[(~(in_be32((void *)GPIO0_IR) >> 5)) & 0x0000000f]; |
| 111 | id2 = trans[(~(in_be32((void *)GPIO0_IR) >> 9)) & 0x0000000f]; |
| 112 | printf(" (ID=0x%1X%1X, PLD=0x%02X)\n", |
| 113 | id2, id1, in_8((void *)0xf0001000)); |
stroese | de46bb6 | 2003-09-12 08:41:24 +0000 | [diff] [blame] | 114 | |
| 115 | return 0; |
| 116 | } |