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git01.mediatek.com / filogic / uboot / dc2c4f06b2bcbe6f7a99ade5022322858f0d4f9b / . / board / LaCie / netspace_v2 / netspace_v2.c
blob: 17e629622ff733487303611f58730835e1317246 [file] [log] [blame]
Simon Guinot16311a22011-06-17 19:41:33 +0530[diff] [blame]1/*
2 * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
3 *
4 * Based on Kirkwood support:
5 * (C) Copyright 2009
6 * Marvell Semiconductor <www.marvell.com>
7 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
8 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]9 * SPDX-License-Identifier: GPL-2.0+
Simon Guinot16311a22011-06-17 19:41:33 +0530[diff] [blame]10 */
11
12#include <common.h>
Simon Guinot16311a22011-06-17 19:41:33 +0530[diff] [blame]13#include <command.h>
Anatolij Gustschin5cf80f12011-10-29 11:31:19 +0000[diff] [blame]14#include <asm/arch/cpu.h>
Stefan Roesec2437842014-10-22 12:13:06 +0200[diff] [blame]15#include <asm/arch/soc.h>
Simon Guinot16311a22011-06-17 19:41:33 +0530[diff] [blame]16#include <asm/arch/mpp.h>
17#include <asm/arch/gpio.h>
Simon Guinota35cb4c2011-11-21 19:25:47 +0530[diff] [blame]18
Simon Guinot16311a22011-06-17 19:41:33 +0530[diff] [blame]19#include "netspace_v2.h"
Simon Guinota35cb4c2011-11-21 19:25:47 +0530[diff] [blame]20#include "../common/common.h"
Simon Guinot16311a22011-06-17 19:41:33 +0530[diff] [blame]21
22DECLARE_GLOBAL_DATA_PTR;
23
24int board_early_init_f(void)
25{
26 /* Gpio configuration */
Stefan Roesec50ab392014-10-22 12:13:11 +0200[diff] [blame]27 mvebu_config_gpio(NETSPACE_V2_OE_VAL_LOW, NETSPACE_V2_OE_VAL_HIGH,
28 NETSPACE_V2_OE_LOW, NETSPACE_V2_OE_HIGH);
Simon Guinot16311a22011-06-17 19:41:33 +0530[diff] [blame]29
30 /* Multi-Purpose Pins Functionality configuration */
Albert ARIBAUD4d424312012-11-26 11:27:36 +0000[diff] [blame]31 static const u32 kwmpp_config[] = {
Simon Guinot16311a22011-06-17 19:41:33 +0530[diff] [blame]32 MPP0_SPI_SCn,
33 MPP1_SPI_MOSI,
34 MPP2_SPI_SCK,
35 MPP3_SPI_MISO,
36 MPP4_NF_IO6,
37 MPP5_NF_IO7,
38 MPP6_SYSRST_OUTn,
39 MPP7_GPO, /* Fan speed (bit 1) */
40 MPP8_TW_SDA,
41 MPP9_TW_SCK,
42 MPP10_UART0_TXD,
43 MPP11_UART0_RXD,
44 MPP12_GPO, /* Red led */
45 MPP14_GPIO, /* USB fuse */
46 MPP16_GPIO, /* SATA 0 power */
47 MPP17_GPIO, /* SATA 1 power */
48 MPP18_NF_IO0,
49 MPP19_NF_IO1,
50 MPP20_SATA1_ACTn,
51 MPP21_SATA0_ACTn,
52 MPP22_GPIO, /* Fan speed (bit 0) */
53 MPP23_GPIO, /* Fan power */
54 MPP24_GPIO, /* USB mode select */
55 MPP25_GPIO, /* Fan rotation fail */
56 MPP26_GPIO, /* USB vbus-in detection */
57 MPP28_GPIO, /* USB enable vbus-out */
58 MPP29_GPIO, /* Blue led (slow register) */
59 MPP30_GPIO, /* Blue led (command register) */
60 MPP31_GPIO, /* Board power off */
61 MPP32_GPIO, /* Button (0 = Released, 1 = Pushed) */
62 MPP33_GPIO, /* Fan speed (bit 2) */
63 0
64 };
Valentin Longchamp7d0d5022012-06-01 01:31:00 +0000[diff] [blame]65 kirkwood_mpp_conf(kwmpp_config, NULL);
Simon Guinot16311a22011-06-17 19:41:33 +0530[diff] [blame]66
67 return 0;
68}
69
70int board_init(void)
71{
72 /* Machine number */
73 gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
74
75 /* Boot parameters address */
Stefan Roese0b741752014-10-22 12:13:13 +0200[diff] [blame]76 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
Simon Guinot16311a22011-06-17 19:41:33 +0530[diff] [blame]77
78 return 0;
79}
80
Simon Guinota35cb4c2011-11-21 19:25:47 +0530[diff] [blame]81#if defined(CONFIG_MISC_INIT_R)
Simon Guinot6e238912011-11-08 11:31:14 +0000[diff] [blame]82int misc_init_r(void)
83{
84#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
85 if (!getenv("ethaddr")) {
Simon Guinot6e238912011-11-08 11:31:14 +0000[diff] [blame]86 uchar mac[6];
Simon Guinota35cb4c2011-11-21 19:25:47 +0530[diff] [blame]87 if (lacie_read_mac_address(mac) == 0)
88 eth_setenv_enetaddr("ethaddr", mac);
Simon Guinot6e238912011-11-08 11:31:14 +0000[diff] [blame]89 }
Simon Guinota35cb4c2011-11-21 19:25:47 +0530[diff] [blame]90#endif
Simon Guinot6e238912011-11-08 11:31:14 +0000[diff] [blame]91 return 0;
92}
Simon Guinota35cb4c2011-11-21 19:25:47 +0530[diff] [blame]93#endif
Simon Guinot16311a22011-06-17 19:41:33 +0530[diff] [blame]94
Simon Guinota35cb4c2011-11-21 19:25:47 +0530[diff] [blame]95#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
Simon Guinot16311a22011-06-17 19:41:33 +0530[diff] [blame]96/* Configure and initialize PHY */
97void reset_phy(void)
98{
Simon Guinot13c5ae62012-09-06 10:51:42 +0000[diff] [blame]99#if defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2)
100 mv_phy_88e1318_init("egiga0", 0);
101#else
Simon Guinot0473b682012-06-05 13:16:00 +0000[diff] [blame]102 mv_phy_88e1116_init("egiga0", 8);
Simon Guinot13c5ae62012-09-06 10:51:42 +0000[diff] [blame]103#endif
Simon Guinot16311a22011-06-17 19:41:33 +0530[diff] [blame]104}
Simon Guinota35cb4c2011-11-21 19:25:47 +0530[diff] [blame]105#endif
Simon Guinot16311a22011-06-17 19:41:33 +0530[diff] [blame]106
Simon Guinota35cb4c2011-11-21 19:25:47 +0530[diff] [blame]107#if defined(CONFIG_KIRKWOOD_GPIO)
Simon Guinot16311a22011-06-17 19:41:33 +0530[diff] [blame]108/* Return GPIO button status */
109static int
110do_read_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
111{
112 return kw_gpio_get_value(NETSPACE_V2_GPIO_BUTTON);
113}
114
115U_BOOT_CMD(button, 1, 1, do_read_button,
116 "Return GPIO button status 0=off 1=on", "");
Simon Guinota35cb4c2011-11-21 19:25:47 +0530[diff] [blame]117#endif