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Stefan Roese42fbddd2006-09-07 11:51:23 +02001/*
Stefan Roese00840322008-03-07 08:01:43 +01002 * (C) Copyright 2006-2008
Stefan Roese42fbddd2006-09-07 11:51:23 +02003 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * (C) Copyright 2006
6 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
7 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
8 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02009 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese42fbddd2006-09-07 11:51:23 +020010 */
11
Larry Johnsonf35b86b2008-01-18 21:49:05 -050012/*
Stefan Roese15adf442007-01-30 17:06:10 +010013 * sequoia.h - configuration for Sequoia & Rainier boards
Larry Johnsonf35b86b2008-01-18 21:49:05 -050014 */
Stefan Roese42fbddd2006-09-07 11:51:23 +020015#ifndef __CONFIG_H
16#define __CONFIG_H
17
Larry Johnsonf35b86b2008-01-18 21:49:05 -050018/*
Stefan Roese42fbddd2006-09-07 11:51:23 +020019 * High Level Configuration Options
Larry Johnsonf35b86b2008-01-18 21:49:05 -050020 */
Stefan Roese15adf442007-01-30 17:06:10 +010021/* This config file is used for Sequoia (440EPx) and Rainier (440GRx) */
Stefan Roesebe6729c2006-09-13 13:51:58 +020022#ifndef CONFIG_RAINIER
Larry Johnsonf35b86b2008-01-18 21:49:05 -050023#define CONFIG_440EPX 1 /* Specific PPC440EPx */
Stefan Roesecfe58022008-06-06 15:55:21 +020024#define CONFIG_HOSTNAME sequoia
Stefan Roesebe6729c2006-09-13 13:51:58 +020025#else
Larry Johnsonf35b86b2008-01-18 21:49:05 -050026#define CONFIG_440GRX 1 /* Specific PPC440GRx */
Stefan Roesecfe58022008-06-06 15:55:21 +020027#define CONFIG_HOSTNAME rainier
Stefan Roesebe6729c2006-09-13 13:51:58 +020028#endif
Larry Johnsonf35b86b2008-01-18 21:49:05 -050029#define CONFIG_440 1 /* ... PPC440 family */
Stefan Roesecfe58022008-06-06 15:55:21 +020030
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020031#ifndef CONFIG_SYS_TEXT_BASE
32#define CONFIG_SYS_TEXT_BASE 0xFFF80000
33#endif
34
Stefan Roesecfe58022008-06-06 15:55:21 +020035/*
36 * Include common defines/options for all AMCC eval boards
37 */
38#include "amcc-common.h"
39
Jeffrey Mann7aa1bb22007-05-05 08:32:14 +020040/* Detect Sequoia PLL input clock automatically via CPLD bit */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020041#define CONFIG_SYS_CLK_FREQ ((in8(CONFIG_SYS_BCSR_BASE + 3) & 0x80) ? \
Jeffrey Mann40e77f32007-05-07 19:42:49 +020042 33333333 : 33000000)
Stefan Roese42fbddd2006-09-07 11:51:23 +020043
Anatolij Gustschin05d5eca2008-02-21 12:52:29 +010044/*
45 * Define this if you want support for video console with radeon 9200 pci card
Wolfgang Denk0708bc62010-10-07 21:51:12 +020046 * Also set CONFIG_SYS_TEXT_BASE to 0xFFF80000 in board/amcc/sequoia/config.mk in this case
Anatolij Gustschin05d5eca2008-02-21 12:52:29 +010047 */
Anatolij Gustschin05d5eca2008-02-21 12:52:29 +010048
49#ifdef CONFIG_VIDEO
Stefan Roesef3727512007-10-31 17:57:52 +010050/*
51 * 44x dcache supported is working now on sequoia, but we don't enable
52 * it yet since it needs further testing
53 */
Larry Johnsonf35b86b2008-01-18 21:49:05 -050054#define CONFIG_4xx_DCACHE /* enable dcache */
Stefan Roesef3727512007-10-31 17:57:52 +010055#endif
56
Larry Johnsonf35b86b2008-01-18 21:49:05 -050057#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
Stefan Roese42fbddd2006-09-07 11:51:23 +020058
Larry Johnsonf35b86b2008-01-18 21:49:05 -050059/*
60 * Base addresses -- Note these are effective addresses where the actual
61 * resources get mapped (not physical addresses).
62 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020063#define CONFIG_SYS_TLB_FOR_BOOT_FLASH 0x0003
64#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
65#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */
66#define CONFIG_SYS_NAND_ADDR 0xd0000000 /* NAND Flash */
67#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
68#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE
69#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
70#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
71#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
72#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
73#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
Stefan Roese42fbddd2006-09-07 11:51:23 +020074
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020075#define CONFIG_SYS_USB2D0_BASE 0xe0000100
76#define CONFIG_SYS_USB_DEVICE 0xe0000000
77#define CONFIG_SYS_USB_HOST 0xe0000400
78#define CONFIG_SYS_BCSR_BASE 0xc0000000
Stefan Roese42fbddd2006-09-07 11:51:23 +020079
Larry Johnsonf35b86b2008-01-18 21:49:05 -050080/*
Stefan Roese42fbddd2006-09-07 11:51:23 +020081 * Initial RAM & stack pointer
Larry Johnsonf35b86b2008-01-18 21:49:05 -050082 */
Stefan Roese42fbddd2006-09-07 11:51:23 +020083/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020084#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +020085#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
Wolfgang Denk0191e472010-10-26 14:34:52 +020086#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Michael Zaidmanf969a682010-09-20 08:51:53 +020087#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
Stefan Roese42fbddd2006-09-07 11:51:23 +020088
Larry Johnsonf35b86b2008-01-18 21:49:05 -050089/*
Stefan Roese42fbddd2006-09-07 11:51:23 +020090 * Serial Port
Larry Johnsonf35b86b2008-01-18 21:49:05 -050091 */
Stefan Roese3ddce572010-09-20 16:05:31 +020092#define CONFIG_CONS_INDEX 1 /* Use UART0 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020093#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
Stefan Roese42fbddd2006-09-07 11:51:23 +020094
Larry Johnsonf35b86b2008-01-18 21:49:05 -050095/*
Stefan Roese42fbddd2006-09-07 11:51:23 +020096 * Environment
Larry Johnsonf35b86b2008-01-18 21:49:05 -050097 */
Stefan Roeseb3859f22014-03-04 15:34:35 +010098#if defined(CONFIG_SYS_RAMBOOT)
Stefan Roesec20ef322009-05-11 13:46:14 +020099#define CONFIG_ENV_IS_NOWHERE /* Store env in memory only */
100#define CONFIG_ENV_SIZE (8 << 10)
Stefan Roese42fbddd2006-09-07 11:51:23 +0200101#else
Stefan Roesec20ef322009-05-11 13:46:14 +0200102#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environ vars */
Stefan Roese42fbddd2006-09-07 11:51:23 +0200103#endif
Stefan Roese42fbddd2006-09-07 11:51:23 +0200104
Stefan Roesec20ef322009-05-11 13:46:14 +0200105#if defined(CONFIG_CMD_FLASH)
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500106/*
Stefan Roese42fbddd2006-09-07 11:51:23 +0200107 * FLASH related
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500108 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200109#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200110#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
Stefan Roese42fbddd2006-09-07 11:51:23 +0200111
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200112#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
Stefan Roese42fbddd2006-09-07 11:51:23 +0200113
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200114#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
115#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
Stefan Roese42fbddd2006-09-07 11:51:23 +0200116
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200117#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
118#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Stefan Roese42fbddd2006-09-07 11:51:23 +0200119
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200120#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
121#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
Stefan Roese42fbddd2006-09-07 11:51:23 +0200122
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200123#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
124#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
Joe Hershberger5a9d7f12015-06-22 16:15:30 -0500125#endif /* CONFIG_CMD_FLASH */
Stefan Roese42fbddd2006-09-07 11:51:23 +0200126
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200127#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200128#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200129#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200130#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
Stefan Roese42fbddd2006-09-07 11:51:23 +0200131
132/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200133#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
134#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Stefan Roese42fbddd2006-09-07 11:51:23 +0200135#endif
136
Stefan Roese42fbddd2006-09-07 11:51:23 +0200137/*
Stefan Roese42fbddd2006-09-07 11:51:23 +0200138 * DDR SDRAM
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500139 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200140#define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */
Stefan Roeseb3859f22014-03-04 15:34:35 +0100141#if !defined(CONFIG_SYS_RAMBOOT)
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500142#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
Stefan Roese5684da02007-01-05 10:38:05 +0100143#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200144#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
Stefan Roesea13709f2008-03-26 10:14:11 +0100145 /* 440EPx errata CHIP 11 */
Stefan Roese42fbddd2006-09-07 11:51:23 +0200146
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500147/*
Stefan Roese42fbddd2006-09-07 11:51:23 +0200148 * I2C
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500149 */
Dirk Eibach42b204f2013-04-25 02:40:01 +0000150#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
Stefan Roese42fbddd2006-09-07 11:51:23 +0200151
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200152#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
153#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
154#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
155#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
Stefan Roese42fbddd2006-09-07 11:51:23 +0200156
Stefan Roeseef28e732009-10-19 16:19:36 +0200157/* I2C bootstrap EEPROM */
158#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52
159#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
160#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
161
Stefan Roese42fbddd2006-09-07 11:51:23 +0200162/* I2C SYSMON (LM75, AD7414 is almost compatible) */
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500163#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
164#define CONFIG_DTT_AD7414 1 /* use AD7414 */
165#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200166#define CONFIG_SYS_DTT_MAX_TEMP 70
167#define CONFIG_SYS_DTT_LOW_TEMP -30
168#define CONFIG_SYS_DTT_HYSTERESIS 3
Stefan Roese42fbddd2006-09-07 11:51:23 +0200169
Stefan Roesecfe58022008-06-06 15:55:21 +0200170/*
171 * Default environment variables
172 */
Stefan Roese42fbddd2006-09-07 11:51:23 +0200173#define CONFIG_EXTRA_ENV_SETTINGS \
Stefan Roesecfe58022008-06-06 15:55:21 +0200174 CONFIG_AMCC_DEF_ENV \
175 CONFIG_AMCC_DEF_ENV_POWERPC \
176 CONFIG_AMCC_DEF_ENV_PPC_OLD \
177 CONFIG_AMCC_DEF_ENV_NOR_UPD \
Stefan Roese38a91762006-11-20 20:39:52 +0100178 "kernel_addr=FC000000\0" \
179 "ramdisk_addr=FC180000\0" \
Stefan Roese42fbddd2006-09-07 11:51:23 +0200180 ""
Stefan Roese42fbddd2006-09-07 11:51:23 +0200181
182#define CONFIG_M88E1111_PHY 1
183#define CONFIG_IBM_EMAC4_V4 1
Stefan Roese42fbddd2006-09-07 11:51:23 +0200184#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
185
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500186#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
Stefan Roese42fbddd2006-09-07 11:51:23 +0200187#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
188
189#define CONFIG_HAS_ETH0
Stefan Roese42fbddd2006-09-07 11:51:23 +0200190#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
191#define CONFIG_PHY1_ADDR 1
192
193/* USB */
Stefan Roesebe6729c2006-09-13 13:51:58 +0200194#ifdef CONFIG_440EPX
Chris Zhang20f10262010-01-06 13:34:06 -0800195
196#undef CONFIG_USB_EHCI /* OHCI by default */
197
198#ifdef CONFIG_USB_EHCI
199#define CONFIG_USB_EHCI_PPC4XX
200#define CONFIG_SYS_PPC4XX_USB_ADDR 0xe0000300
201#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
202#define CONFIG_EHCI_MMIO_BIG_ENDIAN
203#define CONFIG_EHCI_DESC_BIG_ENDIAN
Chris Zhang20f10262010-01-06 13:34:06 -0800204#else /* CONFIG_USB_EHCI */
Matthias Fuchs12985f82007-11-09 15:37:53 +0100205#define CONFIG_USB_OHCI_NEW
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200206#define CONFIG_SYS_OHCI_BE_CONTROLLER
Matthias Fuchs12985f82007-11-09 15:37:53 +0100207
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200208#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
209#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
210#define CONFIG_SYS_USB_OHCI_REGS_BASE CONFIG_SYS_USB_HOST
211#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440"
212#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
Chris Zhang20f10262010-01-06 13:34:06 -0800213#endif
Stefan Roese42fbddd2006-09-07 11:51:23 +0200214
215/* Comment this out to enable USB 1.1 device */
216#define USB_2_0_DEVICE
217
Stefan Roesebe6729c2006-09-13 13:51:58 +0200218#endif /* CONFIG_440EPX */
219
Stefan Roese42fbddd2006-09-07 11:51:23 +0200220/* Partitions */
221#define CONFIG_MAC_PARTITION
222#define CONFIG_DOS_PARTITION
223#define CONFIG_ISO_PARTITION
224
Jon Loeliger49851be2007-07-04 22:33:30 -0500225/*
Stefan Roesecfe58022008-06-06 15:55:21 +0200226 * Commands additional to the ones defined in amcc-common.h
Jon Loeliger5c4ddae2007-07-10 10:12:10 -0500227 */
Stefan Roeseef28e732009-10-19 16:19:36 +0200228#define CONFIG_CMD_CHIP_CONFIG
Jon Loeliger49851be2007-07-04 22:33:30 -0500229#define CONFIG_CMD_DTT
Jon Loeliger49851be2007-07-04 22:33:30 -0500230#define CONFIG_CMD_NAND
Jon Loeliger49851be2007-07-04 22:33:30 -0500231#define CONFIG_CMD_PCI
Jon Loeliger49851be2007-07-04 22:33:30 -0500232#define CONFIG_CMD_SDRAM
233
234#ifdef CONFIG_440EPX
Jon Loeliger49851be2007-07-04 22:33:30 -0500235#endif
236
Stefan Roesefa840e32007-08-16 10:18:33 +0200237#ifndef CONFIG_RAINIER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200238#define CONFIG_SYS_POST_FPU_ON CONFIG_SYS_POST_FPU
Stefan Roesefa840e32007-08-16 10:18:33 +0200239#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200240#define CONFIG_SYS_POST_FPU_ON 0
Stefan Roesefa840e32007-08-16 10:18:33 +0200241#endif
Stefan Roese42fbddd2006-09-07 11:51:23 +0200242
Stefan Roese376ec7c2009-04-15 14:06:26 +0200243/*
244 * Don't run the memory POST on the NAND-booting version. It will
245 * overwrite part of the U-Boot image which is already loaded from NAND
246 * to SDRAM.
247 */
Stefan Roeseb3859f22014-03-04 15:34:35 +0100248#if defined(CONFIG_SYS_RAMBOOT)
Stefan Roese376ec7c2009-04-15 14:06:26 +0200249#define CONFIG_SYS_POST_MEMORY_ON 0
250#else
251#define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY
252#endif
253
Igor Lisitsin95bcd382007-03-28 19:06:19 +0400254/* POST support */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200255#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
256 CONFIG_SYS_POST_CPU | \
257 CONFIG_SYS_POST_ETHER | \
Stefan Roese376ec7c2009-04-15 14:06:26 +0200258 CONFIG_SYS_POST_FPU_ON | \
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200259 CONFIG_SYS_POST_I2C | \
Stefan Roese376ec7c2009-04-15 14:06:26 +0200260 CONFIG_SYS_POST_MEMORY_ON | \
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200261 CONFIG_SYS_POST_SPR | \
262 CONFIG_SYS_POST_UART)
Igor Lisitsin95bcd382007-03-28 19:06:19 +0400263
Igor Lisitsin95bcd382007-03-28 19:06:19 +0400264#define CONFIG_LOGBUFFER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200265#define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
Igor Lisitsin95bcd382007-03-28 19:06:19 +0400266
Stefan Roese42fbddd2006-09-07 11:51:23 +0200267#define CONFIG_SUPPORT_VFAT
268
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500269/*
Stefan Roese42fbddd2006-09-07 11:51:23 +0200270 * PCI stuff
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500271 */
Stefan Roese42fbddd2006-09-07 11:51:23 +0200272/* General PCI */
Gabor Juhosb4458732013-05-30 07:06:12 +0000273#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200274#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500275#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200276#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */
277 /* CONFIG_SYS_PCI_MEMBASE */
Stefan Roese42fbddd2006-09-07 11:51:23 +0200278/* Board-specific PCI */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200279#define CONFIG_SYS_PCI_TARGET_INIT
280#define CONFIG_SYS_PCI_MASTER_INIT
Stefan Roese5d8033e2009-11-12 16:41:09 +0100281#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
Stefan Roese42fbddd2006-09-07 11:51:23 +0200282
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200283#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
284#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
Stefan Roese42fbddd2006-09-07 11:51:23 +0200285
286/*
Stefan Roese42fbddd2006-09-07 11:51:23 +0200287 * External Bus Controller (EBC) Setup
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500288 */
Stefan Roese42fbddd2006-09-07 11:51:23 +0200289
290/*
291 * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
292 */
Stefan Roeseb3859f22014-03-04 15:34:35 +0100293#if !defined(CONFIG_SYS_RAMBOOT)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200294#define CONFIG_SYS_NAND_CS 3 /* NAND chip connected to CSx */
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500295/* Memory Bank 0 (NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200296#define CONFIG_SYS_EBC_PB0AP 0x03017200
297#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xda000)
Stefan Roese42fbddd2006-09-07 11:51:23 +0200298
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500299/* Memory Bank 3 (NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200300#define CONFIG_SYS_EBC_PB3AP 0x018003c0
301#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
Stefan Roese42fbddd2006-09-07 11:51:23 +0200302#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200303#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500304/* Memory Bank 3 (NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200305#define CONFIG_SYS_EBC_PB3AP 0x03017200
306#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FLASH_BASE | 0xda000)
Stefan Roese42fbddd2006-09-07 11:51:23 +0200307
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500308/* Memory Bank 0 (NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200309#define CONFIG_SYS_EBC_PB0AP 0x018003c0
310#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
Stefan Roese42fbddd2006-09-07 11:51:23 +0200311#endif
312
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500313/* Memory Bank 2 (CPLD) initialization */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200314#define CONFIG_SYS_EBC_PB2AP 0x24814580
315#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_BCSR_BASE | 0x38000)
Stefan Roese42fbddd2006-09-07 11:51:23 +0200316
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200317#define CONFIG_SYS_BCSR5_PCI66EN 0x80
Stefan Roesefa257472007-10-15 11:29:33 +0200318
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500319/*
Stefan Roese3cdd3fd2006-10-20 14:28:52 +0200320 * NAND FLASH
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500321 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200322#define CONFIG_SYS_MAX_NAND_DEVICE 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200323#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
324#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
Stefan Roese3cdd3fd2006-10-20 14:28:52 +0200325
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500326/*
Lawrence R. Johnson1e8db032008-01-04 02:11:56 -0500327 * PPC440 GPIO Configuration
328 */
329/* test-only: take GPIO init from pcs440ep ???? in config file */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200330#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
Lawrence R. Johnson1e8db032008-01-04 02:11:56 -0500331{ \
332/* GPIO Core 0 */ \
333{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
334{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
335{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
336{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
337{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
338{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
339{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
340{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
341{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
342{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
343{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
344{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
345{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
346{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
347{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO14 */ \
348{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \
349{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4) */ \
350{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5) */ \
351{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6) */ \
352{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7) */ \
353{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
354{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
355{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
356{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
357{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2) */ \
358{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3) */ \
359{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
360{GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
361{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO28 USB2D_TXVALID */ \
362{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
363{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
364{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
365}, \
366{ \
367/* GPIO Core 1 */ \
368{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
369{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
Steven A. Falco7bf9cc62008-08-06 15:42:52 -0400370{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO34 UART0_8PIN_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
371{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
372{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO36 UART0_CTS_N EBC_DATA(0) UART3_SIN*/ \
373{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
374{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_8PIN_DTR_N UART1_SOUT */ \
375{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_8PIN_RI_N UART1_SIN */ \
Lawrence R. Johnson1e8db032008-01-04 02:11:56 -0500376{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
377{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
378{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
379{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
380{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
381{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
382{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
383{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
384{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
385{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
386{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
387{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
388{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
389{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
390{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
391{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
392{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
393{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
394{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
395{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
396{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
397{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
398{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
399{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
400} \
401}
402
Anatolij Gustschin05d5eca2008-02-21 12:52:29 +0100403#ifdef CONFIG_VIDEO
404#define CONFIG_BIOSEMU /* x86 bios emulator for vga bios */
405#define CONFIG_ATI_RADEON_FB /* use radeon framebuffer driver */
406#define VIDEO_IO_OFFSET 0xe8000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200407#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
Anatolij Gustschin05d5eca2008-02-21 12:52:29 +0100408#define CONFIG_VIDEO_LOGO
Anatolij Gustschin05d5eca2008-02-21 12:52:29 +0100409#define CONFIG_SPLASH_SCREEN
Anatolij Gustschin05d5eca2008-02-21 12:52:29 +0100410#define CONFIG_CMD_BMP
411#endif
412
Larry Johnsonf35b86b2008-01-18 21:49:05 -0500413#endif /* __CONFIG_H */