stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2001-2003 |
| 3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | /* |
| 25 | * board/config.h - configuration options, board specific |
| 26 | */ |
| 27 | |
| 28 | #ifndef __CONFIG_H |
| 29 | #define __CONFIG_H |
| 30 | |
| 31 | /* |
| 32 | * High Level Configuration Options |
| 33 | * (easy to change) |
| 34 | */ |
| 35 | |
| 36 | #define CONFIG_405EP 1 /* This is a PPC405 CPU */ |
wdenk | da55c6e | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 37 | #define CONFIG_4xx 1 /* ...member of PPC4xx family */ |
| 38 | #define CONFIG_DP405 1 /* ...on a DP405 board */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 39 | |
wdenk | da55c6e | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 40 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ |
| 41 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 42 | |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 43 | #define CONFIG_SYS_CLK_FREQ 33333300 /* external frequency to pll */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 44 | |
| 45 | #define CONFIG_BAUDRATE 9600 |
| 46 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ |
| 47 | |
| 48 | #undef CONFIG_BOOTARGS |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 49 | #undef CONFIG_BOOTCOMMAND |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 50 | |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 51 | #define CONFIG_PREBOOT /* enable preboot variable */ |
| 52 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 53 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 54 | |
Jon Loeliger | f5709d1 | 2007-07-10 09:02:57 -0500 | [diff] [blame] | 55 | /* |
Jon Loeliger | 4e4f207 | 2007-07-07 20:40:43 -0500 | [diff] [blame] | 56 | * Command line configuration. |
| 57 | */ |
| 58 | #include <config_cmd_default.h> |
| 59 | |
| 60 | #define CONFIG_CMD_BSP |
Jon Loeliger | 4e4f207 | 2007-07-07 20:40:43 -0500 | [diff] [blame] | 61 | #define CONFIG_CMD_ELF |
Jon Loeliger | 4e4f207 | 2007-07-07 20:40:43 -0500 | [diff] [blame] | 62 | #define CONFIG_CMD_I2C |
| 63 | #define CONFIG_CMD_EEPROM |
| 64 | |
Matthias Fuchs | a020cee | 2009-04-29 09:51:00 +0200 | [diff] [blame] | 65 | #undef CONFIG_CMD_NET |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 66 | |
wdenk | da55c6e | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 67 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 68 | |
wdenk | da55c6e | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 69 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 70 | |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 71 | #define CONFIG_PRAM 2 /* reserve 2 kB "protected RAM" */ |
| 72 | |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 73 | /* |
| 74 | * Miscellaneous configurable options |
| 75 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 76 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 77 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 78 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 79 | #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
| 80 | #ifdef CONFIG_SYS_HUSH_PARSER |
| 81 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 82 | #endif |
| 83 | |
Jon Loeliger | 4e4f207 | 2007-07-07 20:40:43 -0500 | [diff] [blame] | 84 | #if defined(CONFIG_CMD_KGDB) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 85 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 86 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 87 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 88 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 89 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 90 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 91 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 92 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 93 | #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 94 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 95 | #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 96 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 97 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
| 98 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 99 | |
Stefan Roese | 3ddce57 | 2010-09-20 16:05:31 +0200 | [diff] [blame] | 100 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
| 101 | #define CONFIG_SYS_NS16550 |
| 102 | #define CONFIG_SYS_NS16550_SERIAL |
| 103 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 104 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() |
| 105 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 106 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 107 | #define CONFIG_SYS_BASE_BAUD 691200 |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 108 | |
| 109 | /* The following table includes the supported baudrates */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 110 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 111 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ |
| 112 | 57600, 115200, 230400, 460800, 921600 } |
| 113 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 114 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
| 115 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 116 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 117 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 118 | |
| 119 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
| 120 | |
wdenk | da55c6e | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 121 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 122 | |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 123 | /* |
| 124 | * For booting Linux, the board info and command line data |
| 125 | * have to be in the first 8 MB of memory, since this is |
| 126 | * the maximum mapped by the Linux kernel during initialization. |
| 127 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 128 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 129 | /*----------------------------------------------------------------------- |
| 130 | * FLASH organization |
| 131 | */ |
| 132 | #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ |
| 133 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 134 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
| 135 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 136 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 137 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
| 138 | #define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 139 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 140 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ |
| 141 | #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ |
| 142 | #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 143 | /* |
| 144 | * The following defines are added for buggy IOP480 byte interface. |
| 145 | * All other boards should use the standard values (CPCI405 etc.) |
| 146 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 147 | #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ |
| 148 | #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ |
| 149 | #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 150 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 151 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 152 | |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 153 | /*----------------------------------------------------------------------- |
| 154 | * Start addresses for the final memory configuration |
| 155 | * (Set up by the startup code) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 156 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 157 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 158 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
Matthias Fuchs | a020cee | 2009-04-29 09:51:00 +0200 | [diff] [blame] | 159 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE |
| 160 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE |
| 161 | #define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1) |
| 162 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 163 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 164 | #if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM) |
| 165 | # define CONFIG_SYS_RAMBOOT 1 |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 166 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 167 | # undef CONFIG_SYS_RAMBOOT |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 168 | #endif |
| 169 | |
| 170 | /*----------------------------------------------------------------------- |
| 171 | * Environment Variable setup |
| 172 | */ |
Jean-Christophe PLAGNIOL-VILLARD | e46af64 | 2008-09-05 09:19:30 +0200 | [diff] [blame] | 173 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 174 | #define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ |
| 175 | #define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 176 | /* total size of a CAT24WC16 is 2048 bytes */ |
| 177 | |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 178 | /*----------------------------------------------------------------------- |
| 179 | * I2C EEPROM (CAT24WC16) for environment |
| 180 | */ |
| 181 | #define CONFIG_HARD_I2C /* I2c with hardware support */ |
Stefan Roese | 3b01e6b | 2010-04-01 14:37:24 +0200 | [diff] [blame] | 182 | #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 183 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
| 184 | #define CONFIG_SYS_I2C_SLAVE 0x7F |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 185 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 186 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ |
| 187 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ |
wdenk | da55c6e | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 188 | /* mask of address bits that overflow into the "EEPROM chip address" */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 189 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
| 190 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 191 | /* 16 byte page write mode using*/ |
wdenk | da55c6e | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 192 | /* last 4 bits of the address */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 193 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 194 | |
| 195 | /*----------------------------------------------------------------------- |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 196 | * External Bus Controller (EBC) Setup |
| 197 | */ |
| 198 | |
wdenk | da55c6e | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 199 | #define CAN_BA 0xF0000000 /* CAN Base Address */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 200 | |
wdenk | da55c6e | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 201 | /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 202 | #define CONFIG_SYS_EBC_PB0AP 0x92015480 |
| 203 | #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 204 | |
wdenk | da55c6e | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 205 | /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 206 | #define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
| 207 | #define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 208 | |
| 209 | /*----------------------------------------------------------------------- |
| 210 | * FPGA stuff |
| 211 | */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 212 | /* FPGA program pin configuration */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 213 | #define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */ |
| 214 | #define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */ |
| 215 | #define CONFIG_SYS_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */ |
| 216 | #define CONFIG_SYS_FPGA_INIT 0x00010000 /* unused (ppc input) */ |
| 217 | #define CONFIG_SYS_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 218 | |
| 219 | /*----------------------------------------------------------------------- |
| 220 | * Definitions for initial stack pointer and data area (in data cache) |
| 221 | */ |
| 222 | /* use on chip memory ( OCM ) for temperary stack until sdram is tested */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 223 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 224 | |
| 225 | /* On Chip Memory location */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 226 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 |
| 227 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 |
| 228 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ |
| 229 | #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 230 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 231 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
| 232 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) |
| 233 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 234 | |
| 235 | /*----------------------------------------------------------------------- |
| 236 | * Definitions for GPIO setup (PPC405EP specific) |
| 237 | * |
wdenk | da55c6e | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 238 | * GPIO0[0] - External Bus Controller BLAST output |
| 239 | * GPIO0[1-9] - Instruction trace outputs -> GPIO |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 240 | * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs |
| 241 | * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO |
| 242 | * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs |
| 243 | * GPIO0[24-27] - UART0 control signal inputs/outputs |
| 244 | * GPIO0[28-29] - UART1 data signal input/output |
| 245 | * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs |
| 246 | */ |
wdenk | da55c6e | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 247 | /* GPIO Input: OSR=00, ISR=00, TSR=00, TCR=0 */ |
| 248 | /* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */ |
| 249 | /* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 250 | /* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */ |
Stefan Roese | 8cb251a | 2010-09-12 06:21:37 +0200 | [diff] [blame] | 251 | #define CONFIG_SYS_GPIO0_OSRL 0x40000540 /* 0 ... 15 */ |
| 252 | #define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* 16 ... 31 */ |
| 253 | #define CONFIG_SYS_GPIO0_ISR1L 0x00000000 /* 0 ... 15 */ |
| 254 | #define CONFIG_SYS_GPIO0_ISR1H 0x14000045 /* 16 ... 31 */ |
| 255 | #define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 0 ... 15 */ |
| 256 | #define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 16 ... 31 */ |
Matthias Fuchs | a020cee | 2009-04-29 09:51:00 +0200 | [diff] [blame] | 257 | #define CONFIG_SYS_GPIO0_TCR 0xB7FE0014 /* 0 ... 31 */ |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 258 | |
| 259 | /* |
| 260 | * Internal Definitions |
| 261 | * |
| 262 | * Boot Flags |
| 263 | */ |
| 264 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
| 265 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ |
| 266 | |
| 267 | /* |
| 268 | * Default speed selection (cpu_plb_opb_ebc) in mhz. |
| 269 | * This value will be set if iic boot eprom is disabled. |
| 270 | */ |
wdenk | da55c6e | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 271 | #define PLLMR0_DEFAULT PLLMR0_133_66_66_33 |
| 272 | #define PLLMR1_DEFAULT PLLMR1_133_66_66_33 |
stroese | 446fa1a | 2003-09-12 08:55:18 +0000 | [diff] [blame] | 273 | |
| 274 | #endif /* __CONFIG_H */ |