wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 1 | /* |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 2 | * (C) Copyright 2001-2004 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
| 5 | * (C) Copyright 2002 |
| 6 | * David Mueller, ELSOFT AG, d.mueller@elsoft.ch |
| 7 | * |
| 8 | * See file CREDITS for list of people who contributed to this |
| 9 | * project. |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or |
| 12 | * modify it under the terms of the GNU General Public License as |
| 13 | * published by the Free Software Foundation; either version 2 of |
| 14 | * the License, or (at your option) any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; if not, write to the Free Software |
| 23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 24 | * MA 02111-1307 USA |
| 25 | */ |
| 26 | |
| 27 | /* This code should work for both the S3C2400 and the S3C2410 |
| 28 | * as they seem to have the same PLL and clock machinery inside. |
| 29 | * The different address mapping is handled by the s3c24xx.h files below. |
| 30 | */ |
| 31 | |
| 32 | #include <common.h> |
kevin.morfitt@fearnside-systems.co.uk | e0d8131 | 2009-11-17 18:30:34 +0900 | [diff] [blame] | 33 | #ifdef CONFIG_S3C24X0 |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 34 | |
kevin.morfitt@fearnside-systems.co.uk | d1cacc7 | 2009-10-10 13:30:22 +0900 | [diff] [blame] | 35 | #include <asm/io.h> |
kevin.morfitt@fearnside-systems.co.uk | e0d8131 | 2009-11-17 18:30:34 +0900 | [diff] [blame] | 36 | #include <asm/arch/s3c24x0_cpu.h> |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 37 | |
| 38 | #define MPLL 0 |
| 39 | #define UPLL 1 |
| 40 | |
| 41 | /* ------------------------------------------------------------------------- */ |
| 42 | /* NOTE: This describes the proper use of this file. |
| 43 | * |
wdenk | 1272e23 | 2002-11-10 22:06:23 +0000 | [diff] [blame] | 44 | * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL. |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 45 | * |
| 46 | * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of |
| 47 | * the specified bus in HZ. |
| 48 | */ |
| 49 | /* ------------------------------------------------------------------------- */ |
| 50 | |
| 51 | static ulong get_PLLCLK(int pllreg) |
| 52 | { |
kevin.morfitt@fearnside-systems.co.uk | d1cacc7 | 2009-10-10 13:30:22 +0900 | [diff] [blame] | 53 | struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); |
| 54 | ulong r, m, p, s; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 55 | |
kevin.morfitt@fearnside-systems.co.uk | d1cacc7 | 2009-10-10 13:30:22 +0900 | [diff] [blame] | 56 | if (pllreg == MPLL) |
| 57 | r = readl(&clk_power->MPLLCON); |
| 58 | else if (pllreg == UPLL) |
| 59 | r = readl(&clk_power->UPLLCON); |
| 60 | else |
| 61 | hang(); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 62 | |
kevin.morfitt@fearnside-systems.co.uk | d1cacc7 | 2009-10-10 13:30:22 +0900 | [diff] [blame] | 63 | m = ((r & 0xFF000) >> 12) + 8; |
| 64 | p = ((r & 0x003F0) >> 4) + 2; |
| 65 | s = r & 0x3; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 66 | |
kevin.morfitt@fearnside-systems.co.uk | d1cacc7 | 2009-10-10 13:30:22 +0900 | [diff] [blame] | 67 | return (CONFIG_SYS_CLK_FREQ * m) / (p << s); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 68 | } |
| 69 | |
| 70 | /* return FCLK frequency */ |
| 71 | ulong get_FCLK(void) |
| 72 | { |
kevin.morfitt@fearnside-systems.co.uk | d1cacc7 | 2009-10-10 13:30:22 +0900 | [diff] [blame] | 73 | return get_PLLCLK(MPLL); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 74 | } |
| 75 | |
| 76 | /* return HCLK frequency */ |
| 77 | ulong get_HCLK(void) |
| 78 | { |
kevin.morfitt@fearnside-systems.co.uk | d1cacc7 | 2009-10-10 13:30:22 +0900 | [diff] [blame] | 79 | struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 80 | |
kevin.morfitt@fearnside-systems.co.uk | d1cacc7 | 2009-10-10 13:30:22 +0900 | [diff] [blame] | 81 | return (readl(&clk_power->CLKDIVN) & 2) ? get_FCLK() / 2 : get_FCLK(); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 82 | } |
| 83 | |
| 84 | /* return PCLK frequency */ |
| 85 | ulong get_PCLK(void) |
| 86 | { |
kevin.morfitt@fearnside-systems.co.uk | d1cacc7 | 2009-10-10 13:30:22 +0900 | [diff] [blame] | 87 | struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 88 | |
kevin.morfitt@fearnside-systems.co.uk | d1cacc7 | 2009-10-10 13:30:22 +0900 | [diff] [blame] | 89 | return (readl(&clk_power->CLKDIVN) & 1) ? get_HCLK() / 2 : get_HCLK(); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 90 | } |
| 91 | |
| 92 | /* return UCLK frequency */ |
| 93 | ulong get_UCLK(void) |
| 94 | { |
kevin.morfitt@fearnside-systems.co.uk | d1cacc7 | 2009-10-10 13:30:22 +0900 | [diff] [blame] | 95 | return get_PLLCLK(UPLL); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 96 | } |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 97 | |
kevin.morfitt@fearnside-systems.co.uk | e0d8131 | 2009-11-17 18:30:34 +0900 | [diff] [blame] | 98 | #endif /* CONFIG_S3C24X0 */ |