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Haavard Skinnemoen2f5bfb72008-05-16 11:10:33 +02001/*
2 * SPI flash internal definitions
3 *
4 * Copyright (C) 2008 Atmel Corporation
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +05305 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
6 *
Jagannadha Sutradharudu Tekid1452702013-10-10 22:32:55 +05307 * SPDX-License-Identifier: GPL-2.0+
Haavard Skinnemoen2f5bfb72008-05-16 11:10:33 +02008 */
9
Jagannadha Sutradharudu Teki84fb8632013-10-10 22:14:09 +053010#ifndef _SF_INTERNAL_H_
11#define _SF_INTERNAL_H_
Haavard Skinnemoen2f5bfb72008-05-16 11:10:33 +020012
Simon Glassd34b4562014-10-13 23:42:04 -060013#include <linux/types.h>
14#include <linux/compiler.h>
15
16/* Dual SPI flash memories - see SPI_COMM_DUAL_... */
17enum spi_dual_flash {
18 SF_SINGLE_FLASH = 0,
19 SF_DUAL_STACKED_FLASH = 1 << 0,
20 SF_DUAL_PARALLEL_FLASH = 1 << 1,
21};
22
23/* Enum list - Full read commands */
24enum spi_read_cmds {
25 ARRAY_SLOW = 1 << 0,
Jagannadha Sutradharudu Teki29e63912014-12-12 19:36:11 +053026 ARRAY_FAST = 1 << 1,
27 DUAL_OUTPUT_FAST = 1 << 2,
28 DUAL_IO_FAST = 1 << 3,
29 QUAD_OUTPUT_FAST = 1 << 4,
30 QUAD_IO_FAST = 1 << 5,
Simon Glassd34b4562014-10-13 23:42:04 -060031};
32
Jagannadha Sutradharudu Teki29e63912014-12-12 19:36:11 +053033/* Normal - Extended - Full command set */
34#define RD_NORM (ARRAY_SLOW | ARRAY_FAST)
35#define RD_EXTN (RD_NORM | DUAL_OUTPUT_FAST | DUAL_IO_FAST)
Simon Glassd34b4562014-10-13 23:42:04 -060036#define RD_FULL (RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST)
37
38/* sf param flags */
39enum {
40 SECT_4K = 1 << 0,
41 SECT_32K = 1 << 1,
42 E_FSR = 1 << 2,
Jagannadha Sutradharudu Teki7f0fd702014-12-12 19:36:14 +053043 SST_BP = 1 << 3,
Simon Glass52c62bb2014-12-12 19:36:12 +053044 SST_WP = 1 << 4,
Jagannadha Sutradharudu Teki7f0fd702014-12-12 19:36:14 +053045 WR_QPP = 1 << 5,
Simon Glassd34b4562014-10-13 23:42:04 -060046};
47
Jagannadha Sutradharudu Teki7f0fd702014-12-12 19:36:14 +053048#define SST_WR (SST_BP | SST_WP)
49
Jagannadha Sutradharudu Tekica799862014-01-11 16:50:45 +053050#define SPI_FLASH_3B_ADDR_LEN 3
51#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN)
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +053052#define SPI_FLASH_16MB_BOUN 0x1000000
Haavard Skinnemoen2f5bfb72008-05-16 11:10:33 +020053
Jagannadha Sutradharudu Teki725c64e2013-12-26 13:54:57 +053054/* CFI Manufacture ID's */
55#define SPI_FLASH_CFI_MFR_SPANSION 0x01
56#define SPI_FLASH_CFI_MFR_STMICRO 0x20
Jagannadha Sutradharudu Teki754c73c2013-12-26 14:13:36 +053057#define SPI_FLASH_CFI_MFR_MACRONIX 0xc2
Jagannadha Sutradharudu Teki725c64e2013-12-26 13:54:57 +053058#define SPI_FLASH_CFI_MFR_WINBOND 0xef
59
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +053060/* Erase commands */
61#define CMD_ERASE_4K 0x20
62#define CMD_ERASE_32K 0x52
63#define CMD_ERASE_CHIP 0xc7
64#define CMD_ERASE_64K 0xd8
65
66/* Write commands */
Mike Frysinger1302bec2012-01-28 16:26:03 -080067#define CMD_WRITE_STATUS 0x01
Mike Frysinger301e9b42011-04-25 06:58:29 +000068#define CMD_PAGE_PROGRAM 0x02
Mike Frysinger79112112011-04-25 06:59:53 +000069#define CMD_WRITE_DISABLE 0x04
Simon Glassd34b4562014-10-13 23:42:04 -060070#define CMD_READ_STATUS 0x05
Jagannadha Sutradharudu Tekie0ebabc2014-01-11 15:13:11 +053071#define CMD_QUAD_PAGE_PROGRAM 0x32
Mike Frysingerb375ad92013-12-03 16:43:27 -070072#define CMD_READ_STATUS1 0x35
Mike Frysinger53421bb2011-01-10 02:20:13 -050073#define CMD_WRITE_ENABLE 0x06
Simon Glassd34b4562014-10-13 23:42:04 -060074#define CMD_READ_CONFIG 0x35
75#define CMD_FLAG_STATUS 0x70
Mike Frysinger37e13bc2011-01-10 02:20:12 -050076
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +053077/* Read commands */
78#define CMD_READ_ARRAY_SLOW 0x03
79#define CMD_READ_ARRAY_FAST 0x0b
Jagannadha Sutradharudu Teki02eee9a2014-01-11 15:10:28 +053080#define CMD_READ_DUAL_OUTPUT_FAST 0x3b
81#define CMD_READ_DUAL_IO_FAST 0xbb
Jagannadha Sutradharudu Tekie0ebabc2014-01-11 15:13:11 +053082#define CMD_READ_QUAD_OUTPUT_FAST 0x6b
Jagannadha Sutradharudu Teki45462302013-12-24 15:24:31 +053083#define CMD_READ_QUAD_IO_FAST 0xeb
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +053084#define CMD_READ_ID 0x9f
Jagannadha Sutradharudu Teki29d70c92013-06-19 15:37:09 +053085
Jagannadha Sutradharudu Tekice08a712013-06-19 15:31:23 +053086/* Bank addr access commands */
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +053087#ifdef CONFIG_SPI_FLASH_BAR
Jagannadha Sutradharudu Tekic6d173d2013-06-19 15:33:58 +053088# define CMD_BANKADDR_BRWR 0x17
89# define CMD_BANKADDR_BRRD 0x16
90# define CMD_EXTNADDR_WREAR 0xC5
91# define CMD_EXTNADDR_RDEAR 0xC8
92#endif
Jagannadha Sutradharudu Tekice08a712013-06-19 15:31:23 +053093
Mike Frysinger37e13bc2011-01-10 02:20:12 -050094/* Common status */
Jagannadha Sutradharudu Teki243ced02014-01-12 21:38:21 +053095#define STATUS_WIP (1 << 0)
Jagannadha Sutradharudu Teki725c64e2013-12-26 13:54:57 +053096#define STATUS_QEB_WINSPAN (1 << 1)
Simon Glassd34b4562014-10-13 23:42:04 -060097#define STATUS_QEB_MXIC (1 << 6)
Jagannadha Sutradharudu Teki243ced02014-01-12 21:38:21 +053098#define STATUS_PEC (1 << 7)
Mike Frysinger37e13bc2011-01-10 02:20:12 -050099
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +0530100/* Flash timeout values */
101#define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ)
Simon Glassd34b4562014-10-13 23:42:04 -0600102#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ)
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +0530103#define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ)
104
105/* SST specific */
106#ifdef CONFIG_SPI_FLASH_SST
Jagannadha Sutradharudu Tekif3b2dd82013-10-07 19:34:56 +0530107# define CMD_SST_BP 0x02 /* Byte Program */
Simon Glassd34b4562014-10-13 23:42:04 -0600108# define CMD_SST_AAI_WP 0xAD /* Auto Address Incr Word Program */
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +0530109
110int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
111 const void *buf);
Bin Mengfcbfc172014-12-12 19:36:13 +0530112int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
113 const void *buf);
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +0530114#endif
115
Simon Glassd34b4562014-10-13 23:42:04 -0600116/**
117 * struct spi_flash_params - SPI/QSPI flash device params structure
118 *
119 * @name: Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO])
120 * @jedec: Device jedec ID (0x[1byte_manuf_id][2byte_dev_id])
121 * @ext_jedec: Device ext_jedec ID
122 * @sector_size: Sector size of this device
123 * @nr_sectors: No.of sectors on this device
124 * @e_rd_cmd: Enum list for read commands
125 * @flags: Important param, for flash specific behaviour
126 */
127struct spi_flash_params {
128 const char *name;
129 u32 jedec;
130 u16 ext_jedec;
131 u32 sector_size;
132 u32 nr_sectors;
133 u8 e_rd_cmd;
134 u16 flags;
135};
136
137extern const struct spi_flash_params spi_flash_params_table[];
138
Haavard Skinnemoen2f5bfb72008-05-16 11:10:33 +0200139/* Send a single-byte command to the device and read the response */
140int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len);
141
142/*
143 * Send a multi-byte command to the device and read the response. Used
144 * for flash array reads, etc.
145 */
146int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd,
147 size_t cmd_len, void *data, size_t data_len);
148
149/*
150 * Send a multi-byte command to the device followed by (optional)
151 * data. Used for programming the flash array, etc.
152 */
153int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len,
154 const void *data, size_t data_len);
155
Mike Frysinger301e9b42011-04-25 06:58:29 +0000156
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +0530157/* Flash erase(sectors) operation, support all possible erase commands */
158int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len);
Jagannadha Sutradharudu Teki08032422013-10-02 19:34:53 +0530159
Jagannadha Sutradharudu Teki564a1262013-12-30 22:16:23 +0530160/* Read the status register */
161int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs);
162
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +0530163/* Program the status register */
Jagannadha Sutradharudu Teki243ced02014-01-12 21:38:21 +0530164int spi_flash_cmd_write_status(struct spi_flash *flash, u8 ws);
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +0530165
Jagannadha Sutradharudu Teki564a1262013-12-30 22:16:23 +0530166/* Read the config register */
167int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc);
Jagannadha Sutradharudu Teki754c73c2013-12-26 14:13:36 +0530168
Jagannadha Sutradharudu Teki564a1262013-12-30 22:16:23 +0530169/* Program the config register */
170int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc);
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +0530171
172/* Enable writing on the SPI flash */
Mike Frysinger8ec7f4c2011-04-23 23:05:55 +0000173static inline int spi_flash_cmd_write_enable(struct spi_flash *flash)
174{
175 return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0);
176}
177
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +0530178/* Disable writing on the SPI flash */
Mike Frysinger79112112011-04-25 06:59:53 +0000179static inline int spi_flash_cmd_write_disable(struct spi_flash *flash)
180{
181 return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0);
182}
183
184/*
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +0530185 * Send the read status command to the device and wait for the wip
186 * (write-in-progress) bit to clear itself.
Haavard Skinnemoen2f5bfb72008-05-16 11:10:33 +0200187 */
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +0530188int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout);
189
Jagannadha Sutradharudu Tekidc78b852013-06-21 19:19:00 +0530190/*
191 * Used for spi_flash write operation
192 * - SPI claim
193 * - spi_flash_cmd_write_enable
194 * - spi_flash_cmd_write
195 * - spi_flash_cmd_wait_ready
196 * - SPI release
197 */
198int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
199 size_t cmd_len, const void *buf, size_t buf_len);
Mike Frysinger37e13bc2011-01-10 02:20:12 -0500200
201/*
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +0530202 * Flash write operation, support all possible write commands.
203 * Write the requested data out breaking it up into multiple write
204 * commands as needed per the write size.
Mike Frysinger37e13bc2011-01-10 02:20:12 -0500205 */
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +0530206int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
207 size_t len, const void *buf);
208
209/*
210 * Same as spi_flash_cmd_read() except it also claims/releases the SPI
211 * bus. Used as common part of the ->read() operation.
212 */
213int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
214 size_t cmd_len, void *data, size_t data_len);
215
216/* Flash read operation, support all possible read commands */
217int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
218 size_t len, void *data);
Mike Frysinger37e13bc2011-01-10 02:20:12 -0500219
Jagannadha Sutradharudu Teki84fb8632013-10-10 22:14:09 +0530220#endif /* _SF_INTERNAL_H_ */