blob: ea0808ab104255ea6cfcff1a1bc99adbbdc81905 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -05001// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/* Copyright (c) 2020-2022 Microchip Technology Inc */
3
4/dts-v1/;
5
6#include "mpfs.dtsi"
7#include "mpfs-polarberry-fabric.dtsi"
8
9/ {
10 model = "Sundance PolarBerry";
11 compatible = "sundance,polarberry", "microchip,mpfs";
12
13 aliases {
14 ethernet0 = &mac1;
15 serial0 = &mmuart0;
16 };
17
18 chosen {
19 stdout-path = "serial0:115200n8";
20 };
21
22 ddrc_cache_lo: memory@80000000 {
23 device_type = "memory";
24 reg = <0x0 0x80000000 0x0 0x2e000000>;
25 };
26
27 ddrc_cache_hi: memory@1000000000 {
28 device_type = "memory";
29 reg = <0x10 0x00000000 0x0 0xC0000000>;
30 };
31};
32
33/*
34 * phy0 is connected to mac0, but the port itself is on the (optional) carrier
35 * board.
36 */
37&mac0 {
38 phy-mode = "sgmii";
39 phy-handle = <&phy0>;
40 status = "disabled";
41};
42
43&mac1 {
44 phy-mode = "sgmii";
45 phy-handle = <&phy1>;
46 status = "okay";
47
48 phy1: ethernet-phy@5 {
49 reg = <5>;
50 };
51
52 phy0: ethernet-phy@4 {
53 reg = <4>;
54 };
55};
56
57&mbox {
58 status = "okay";
59};
60
61&mmc {
62 bus-width = <4>;
63 disable-wp;
64 cap-sd-highspeed;
65 cap-mmc-highspeed;
66 mmc-ddr-1_8v;
67 mmc-hs200-1_8v;
68 sd-uhs-sdr12;
69 sd-uhs-sdr25;
70 sd-uhs-sdr50;
71 sd-uhs-sdr104;
72 status = "okay";
73};
74
75&mmuart0 {
76 status = "okay";
77};
78
79&refclk {
80 clock-frequency = <125000000>;
81};
82
83&rtc {
84 status = "okay";
85};
86
87&syscontroller {
88 status = "okay";
89};