| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2012 Atmel Corporation |
| 4 | * |
| 5 | * Configuation settings for the AT91SAM9X5EK board. |
| Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef __CONFIG_H__ |
| 9 | #define __CONFIG_H__ |
| 10 | |
| Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 11 | /* ARM asynchronous clock */ |
| 12 | #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 |
| 13 | #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ |
| Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 14 | |
| Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 15 | /* general purpose I/O */ |
| Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 16 | |
| Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 17 | /* |
| Tom Rini | ceed5d2 | 2017-05-12 22:33:27 -0400 | [diff] [blame] | 18 | * define CONFIG_USB_EHCI_HCD to enable USB Hi-Speed (aka 2.0) |
| Richard Genoud | 1e34e83 | 2012-11-29 23:18:34 +0000 | [diff] [blame] | 19 | * NB: in this case, USB 1.1 devices won't be recognized. |
| 20 | */ |
| 21 | |
| Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 22 | /* SDRAM */ |
| Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 23 | #define CONFIG_SYS_SDRAM_BASE 0x20000000 |
| 24 | #define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */ |
| 25 | |
| Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 26 | /* DataFlash */ |
| Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 27 | |
| Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 28 | /* NAND flash */ |
| 29 | #ifdef CONFIG_CMD_NAND |
| Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 30 | #define CFG_SYS_NAND_BASE 0x40000000 |
| Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 31 | /* our ALE is AD21 */ |
| Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 32 | #define CFG_SYS_NAND_MASK_ALE (1 << 21) |
| Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 33 | /* our CLE is AD22 */ |
| Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 34 | #define CFG_SYS_NAND_MASK_CLE (1 << 22) |
| 35 | #define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 |
| 36 | #define CFG_SYS_NAND_READY_PIN AT91_PIN_PD5 |
| Tom Rini | 00448d2 | 2017-07-28 21:31:42 -0400 | [diff] [blame] | 37 | #endif |
| 38 | |
| Bo Shen | 9a3b1fe | 2015-03-27 14:23:35 +0800 | [diff] [blame] | 39 | /* SPL */ |
| Bo Shen | 9a3b1fe | 2015-03-27 14:23:35 +0800 | [diff] [blame] | 40 | |
| Bo Shen | 9a3b1fe | 2015-03-27 14:23:35 +0800 | [diff] [blame] | 41 | #define CONFIG_SYS_MASTER_CLOCK 132096000 |
| 42 | #define CONFIG_SYS_AT91_PLLA 0x20c73f03 |
| 43 | #define CONFIG_SYS_MCKR 0x1301 |
| 44 | #define CONFIG_SYS_MCKR_CSS 0x1302 |
| 45 | |
| Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 46 | #endif |