| Angelo Dureghello | aa86be7 | 2019-03-13 21:46:47 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright (c) 2018 Angelo Dureghello <angelo@sysam.it> |
| 4 | */ |
| 5 | |
| 6 | #ifndef __spi_coldfire_h |
| 7 | #define __spi_coldfire_h |
| 8 | |
| 9 | #define MAX_CTAR_REGS 8 |
| 10 | #define MAX_CTAR_FIELDS 8 |
| 11 | |
| 12 | /* |
| Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 13 | * struct coldfire_spi_plat - information about a coldfire spi module |
| Angelo Dureghello | aa86be7 | 2019-03-13 21:46:47 +0100 | [diff] [blame] | 14 | * |
| 15 | * @regs_addr: base address for module registers |
| 16 | * @speed_hz: default SCK frequency |
| 17 | * @mode: default SPI mode |
| 18 | * @num_cs: number of DSPI chipselect signals |
| 19 | */ |
| Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 20 | struct coldfire_spi_plat { |
| Angelo Dureghello | aa86be7 | 2019-03-13 21:46:47 +0100 | [diff] [blame] | 21 | fdt_addr_t regs_addr; |
| 22 | uint speed_hz; |
| 23 | uint mode; |
| 24 | uint num_cs; |
| 25 | uint ctar[MAX_CTAR_REGS][MAX_CTAR_FIELDS]; |
| 26 | }; |
| 27 | |
| 28 | #endif /* __spi_coldfire_h */ |