Andy Fleming | 60ca78b | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 1 | /* |
| 2 | * RealTek PHY drivers |
| 3 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 4 | * SPDX-License-Identifier: GPL-2.0+ |
Andy Fleming | 60ca78b | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 5 | * |
Codrin Ciubotariu | de947a1 | 2015-02-13 14:47:58 +0200 | [diff] [blame] | 6 | * Copyright 2010-2011, 2015 Freescale Semiconductor, Inc. |
Andy Fleming | 60ca78b | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 7 | * author Andy Fleming |
Andy Fleming | 60ca78b | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 8 | */ |
| 9 | #include <config.h> |
| 10 | #include <common.h> |
| 11 | #include <phy.h> |
| 12 | |
| 13 | #define PHY_AUTONEGOTIATE_TIMEOUT 5000 |
| 14 | |
Bhupesh Sharma | 85eb780 | 2013-07-18 13:58:20 +0530 | [diff] [blame] | 15 | /* RTL8211x PHY Status Register */ |
| 16 | #define MIIM_RTL8211x_PHY_STATUS 0x11 |
| 17 | #define MIIM_RTL8211x_PHYSTAT_SPEED 0xc000 |
| 18 | #define MIIM_RTL8211x_PHYSTAT_GBIT 0x8000 |
| 19 | #define MIIM_RTL8211x_PHYSTAT_100 0x4000 |
| 20 | #define MIIM_RTL8211x_PHYSTAT_DUPLEX 0x2000 |
| 21 | #define MIIM_RTL8211x_PHYSTAT_SPDDONE 0x0800 |
| 22 | #define MIIM_RTL8211x_PHYSTAT_LINK 0x0400 |
Andy Fleming | 60ca78b | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 23 | |
Codrin Ciubotariu | de947a1 | 2015-02-13 14:47:58 +0200 | [diff] [blame] | 24 | /* RTL8211x PHY Interrupt Enable Register */ |
| 25 | #define MIIM_RTL8211x_PHY_INER 0x12 |
| 26 | #define MIIM_RTL8211x_PHY_INTR_ENA 0x9f01 |
| 27 | #define MIIM_RTL8211x_PHY_INTR_DIS 0x0000 |
| 28 | |
| 29 | /* RTL8211x PHY Interrupt Status Register */ |
| 30 | #define MIIM_RTL8211x_PHY_INSR 0x13 |
Andy Fleming | 60ca78b | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 31 | |
Bhupesh Sharma | 85eb780 | 2013-07-18 13:58:20 +0530 | [diff] [blame] | 32 | /* RealTek RTL8211x */ |
| 33 | static int rtl8211x_config(struct phy_device *phydev) |
Andy Fleming | 60ca78b | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 34 | { |
| 35 | phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); |
| 36 | |
Codrin Ciubotariu | de947a1 | 2015-02-13 14:47:58 +0200 | [diff] [blame] | 37 | /* mask interrupt at init; if the interrupt is |
| 38 | * needed indeed, it should be explicitly enabled |
| 39 | */ |
| 40 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER, |
| 41 | MIIM_RTL8211x_PHY_INTR_DIS); |
| 42 | |
| 43 | /* read interrupt status just to clear it */ |
| 44 | phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER); |
| 45 | |
Andy Fleming | 60ca78b | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 46 | genphy_config_aneg(phydev); |
| 47 | |
| 48 | return 0; |
| 49 | } |
| 50 | |
Bhupesh Sharma | 85eb780 | 2013-07-18 13:58:20 +0530 | [diff] [blame] | 51 | static int rtl8211x_parse_status(struct phy_device *phydev) |
Andy Fleming | 60ca78b | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 52 | { |
| 53 | unsigned int speed; |
| 54 | unsigned int mii_reg; |
| 55 | |
Bhupesh Sharma | 85eb780 | 2013-07-18 13:58:20 +0530 | [diff] [blame] | 56 | mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_STATUS); |
Andy Fleming | 60ca78b | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 57 | |
Bhupesh Sharma | 85eb780 | 2013-07-18 13:58:20 +0530 | [diff] [blame] | 58 | if (!(mii_reg & MIIM_RTL8211x_PHYSTAT_SPDDONE)) { |
Andy Fleming | 60ca78b | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 59 | int i = 0; |
| 60 | |
| 61 | /* in case of timeout ->link is cleared */ |
| 62 | phydev->link = 1; |
| 63 | puts("Waiting for PHY realtime link"); |
Bhupesh Sharma | 85eb780 | 2013-07-18 13:58:20 +0530 | [diff] [blame] | 64 | while (!(mii_reg & MIIM_RTL8211x_PHYSTAT_SPDDONE)) { |
Andy Fleming | 60ca78b | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 65 | /* Timeout reached ? */ |
| 66 | if (i > PHY_AUTONEGOTIATE_TIMEOUT) { |
| 67 | puts(" TIMEOUT !\n"); |
| 68 | phydev->link = 0; |
| 69 | break; |
| 70 | } |
| 71 | |
| 72 | if ((i++ % 1000) == 0) |
| 73 | putc('.'); |
| 74 | udelay(1000); /* 1 ms */ |
| 75 | mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, |
Bhupesh Sharma | 85eb780 | 2013-07-18 13:58:20 +0530 | [diff] [blame] | 76 | MIIM_RTL8211x_PHY_STATUS); |
Andy Fleming | 60ca78b | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 77 | } |
| 78 | puts(" done\n"); |
| 79 | udelay(500000); /* another 500 ms (results in faster booting) */ |
| 80 | } else { |
Bhupesh Sharma | 85eb780 | 2013-07-18 13:58:20 +0530 | [diff] [blame] | 81 | if (mii_reg & MIIM_RTL8211x_PHYSTAT_LINK) |
Andy Fleming | 60ca78b | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 82 | phydev->link = 1; |
| 83 | else |
| 84 | phydev->link = 0; |
| 85 | } |
| 86 | |
Bhupesh Sharma | 85eb780 | 2013-07-18 13:58:20 +0530 | [diff] [blame] | 87 | if (mii_reg & MIIM_RTL8211x_PHYSTAT_DUPLEX) |
Andy Fleming | 60ca78b | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 88 | phydev->duplex = DUPLEX_FULL; |
| 89 | else |
| 90 | phydev->duplex = DUPLEX_HALF; |
| 91 | |
Bhupesh Sharma | 85eb780 | 2013-07-18 13:58:20 +0530 | [diff] [blame] | 92 | speed = (mii_reg & MIIM_RTL8211x_PHYSTAT_SPEED); |
Andy Fleming | 60ca78b | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 93 | |
| 94 | switch (speed) { |
Bhupesh Sharma | 85eb780 | 2013-07-18 13:58:20 +0530 | [diff] [blame] | 95 | case MIIM_RTL8211x_PHYSTAT_GBIT: |
Andy Fleming | 60ca78b | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 96 | phydev->speed = SPEED_1000; |
| 97 | break; |
Bhupesh Sharma | 85eb780 | 2013-07-18 13:58:20 +0530 | [diff] [blame] | 98 | case MIIM_RTL8211x_PHYSTAT_100: |
Andy Fleming | 60ca78b | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 99 | phydev->speed = SPEED_100; |
| 100 | break; |
| 101 | default: |
| 102 | phydev->speed = SPEED_10; |
| 103 | } |
| 104 | |
| 105 | return 0; |
| 106 | } |
| 107 | |
Bhupesh Sharma | 85eb780 | 2013-07-18 13:58:20 +0530 | [diff] [blame] | 108 | static int rtl8211x_startup(struct phy_device *phydev) |
Andy Fleming | 60ca78b | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 109 | { |
| 110 | /* Read the Status (2x to make sure link is right) */ |
| 111 | genphy_update_link(phydev); |
Bhupesh Sharma | 85eb780 | 2013-07-18 13:58:20 +0530 | [diff] [blame] | 112 | rtl8211x_parse_status(phydev); |
Andy Fleming | 60ca78b | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 113 | |
| 114 | return 0; |
| 115 | } |
| 116 | |
Bhupesh Sharma | 85eb780 | 2013-07-18 13:58:20 +0530 | [diff] [blame] | 117 | /* Support for RTL8211B PHY */ |
Andy Fleming | 60ca78b | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 118 | static struct phy_driver RTL8211B_driver = { |
| 119 | .name = "RealTek RTL8211B", |
| 120 | .uid = 0x1cc910, |
Bhupesh Sharma | ad4cd95 | 2013-09-01 04:40:52 +0530 | [diff] [blame] | 121 | .mask = 0xffffff, |
Andy Fleming | 60ca78b | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 122 | .features = PHY_GBIT_FEATURES, |
Bhupesh Sharma | 85eb780 | 2013-07-18 13:58:20 +0530 | [diff] [blame] | 123 | .config = &rtl8211x_config, |
| 124 | .startup = &rtl8211x_startup, |
Andy Fleming | 60ca78b | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 125 | .shutdown = &genphy_shutdown, |
| 126 | }; |
| 127 | |
Bhupesh Sharma | 85eb780 | 2013-07-18 13:58:20 +0530 | [diff] [blame] | 128 | /* Support for RTL8211E-VB-CG, RTL8211E-VL-CG and RTL8211EG-VB-CG PHYs */ |
| 129 | static struct phy_driver RTL8211E_driver = { |
| 130 | .name = "RealTek RTL8211E", |
| 131 | .uid = 0x1cc915, |
Bhupesh Sharma | ad4cd95 | 2013-09-01 04:40:52 +0530 | [diff] [blame] | 132 | .mask = 0xffffff, |
Bhupesh Sharma | 85eb780 | 2013-07-18 13:58:20 +0530 | [diff] [blame] | 133 | .features = PHY_GBIT_FEATURES, |
| 134 | .config = &rtl8211x_config, |
| 135 | .startup = &rtl8211x_startup, |
| 136 | .shutdown = &genphy_shutdown, |
| 137 | }; |
| 138 | |
| 139 | /* Support for RTL8211DN PHY */ |
| 140 | static struct phy_driver RTL8211DN_driver = { |
| 141 | .name = "RealTek RTL8211DN", |
| 142 | .uid = 0x1cc914, |
Bhupesh Sharma | ad4cd95 | 2013-09-01 04:40:52 +0530 | [diff] [blame] | 143 | .mask = 0xffffff, |
Bhupesh Sharma | 85eb780 | 2013-07-18 13:58:20 +0530 | [diff] [blame] | 144 | .features = PHY_GBIT_FEATURES, |
| 145 | .config = &rtl8211x_config, |
| 146 | .startup = &rtl8211x_startup, |
| 147 | .shutdown = &genphy_shutdown, |
| 148 | }; |
| 149 | |
Andy Fleming | 60ca78b | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 150 | int phy_realtek_init(void) |
| 151 | { |
| 152 | phy_register(&RTL8211B_driver); |
Bhupesh Sharma | 85eb780 | 2013-07-18 13:58:20 +0530 | [diff] [blame] | 153 | phy_register(&RTL8211E_driver); |
| 154 | phy_register(&RTL8211DN_driver); |
Andy Fleming | 60ca78b | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 155 | |
| 156 | return 0; |
| 157 | } |