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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Stefan Roese5a44c602007-10-21 08:16:12 +02002/*
3 * (C) Copyright 2007
4 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 *
6 * based on a the Linux rtc-x1207.c driver which is:
7 * Copyright 2004 Karen Spearel
8 * Copyright 2005 Alessandro Zummo
9 *
10 * Information and datasheet:
11 * http://www.intersil.com/cda/deviceinfo/0,1477,X1205,00.html
Stefan Roese5a44c602007-10-21 08:16:12 +020012 */
13
14/*
15 * Date & Time support for Xicor/Intersil X1205 RTC
16 */
17
18/* #define DEBUG */
19
20#include <common.h>
21#include <command.h>
22#include <rtc.h>
23#include <i2c.h>
Stefan Roese5a44c602007-10-21 08:16:12 +020024
Stefan Roese5a44c602007-10-21 08:16:12 +020025#define CCR_SEC 0
26#define CCR_MIN 1
27#define CCR_HOUR 2
28#define CCR_MDAY 3
29#define CCR_MONTH 4
30#define CCR_YEAR 5
31#define CCR_WDAY 6
32#define CCR_Y2K 7
33
34#define X1205_REG_SR 0x3F /* status register */
35#define X1205_REG_Y2K 0x37
36#define X1205_REG_DW 0x36
37#define X1205_REG_YR 0x35
38#define X1205_REG_MO 0x34
39#define X1205_REG_DT 0x33
40#define X1205_REG_HR 0x32
41#define X1205_REG_MN 0x31
42#define X1205_REG_SC 0x30
43#define X1205_REG_DTR 0x13
44#define X1205_REG_ATR 0x12
45#define X1205_REG_INT 0x11
46#define X1205_REG_0 0x10
47#define X1205_REG_Y2K1 0x0F
48#define X1205_REG_DWA1 0x0E
49#define X1205_REG_YRA1 0x0D
50#define X1205_REG_MOA1 0x0C
51#define X1205_REG_DTA1 0x0B
52#define X1205_REG_HRA1 0x0A
53#define X1205_REG_MNA1 0x09
54#define X1205_REG_SCA1 0x08
55#define X1205_REG_Y2K0 0x07
56#define X1205_REG_DWA0 0x06
57#define X1205_REG_YRA0 0x05
58#define X1205_REG_MOA0 0x04
59#define X1205_REG_DTA0 0x03
60#define X1205_REG_HRA0 0x02
61#define X1205_REG_MNA0 0x01
62#define X1205_REG_SCA0 0x00
63
64#define X1205_CCR_BASE 0x30 /* Base address of CCR */
65#define X1205_ALM0_BASE 0x00 /* Base address of ALARM0 */
66
67#define X1205_SR_RTCF 0x01 /* Clock failure */
68#define X1205_SR_WEL 0x02 /* Write Enable Latch */
69#define X1205_SR_RWEL 0x04 /* Register Write Enable */
70
71#define X1205_DTR_DTR0 0x01
72#define X1205_DTR_DTR1 0x02
73#define X1205_DTR_DTR2 0x04
74
75#define X1205_HR_MIL 0x80 /* Set in ccr.hour for 24 hr mode */
76
77static void rtc_write(int reg, u8 val)
78{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020079 i2c_write(CONFIG_SYS_I2C_RTC_ADDR, reg, 2, &val, 1);
Stefan Roese5a44c602007-10-21 08:16:12 +020080}
81
82/*
83 * In the routines that deal directly with the x1205 hardware, we use
84 * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch
85 * Epoch is initialized as 2000. Time is set to UTC.
86 */
Yuri Tikhonov9bacd942008-03-20 17:56:04 +030087int rtc_get(struct rtc_time *tm)
Stefan Roese5a44c602007-10-21 08:16:12 +020088{
89 u8 buf[8];
90
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020091 i2c_read(CONFIG_SYS_I2C_RTC_ADDR, X1205_CCR_BASE, 2, buf, 8);
Stefan Roese5a44c602007-10-21 08:16:12 +020092
93 debug("%s: raw read data - sec=%02x, min=%02x, hr=%02x, "
94 "mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n",
95 __FUNCTION__,
96 buf[0], buf[1], buf[2], buf[3],
97 buf[4], buf[5], buf[6], buf[7]);
98
Albin Tonnerre8aca7202009-08-13 15:31:11 +020099 tm->tm_sec = bcd2bin(buf[CCR_SEC]);
100 tm->tm_min = bcd2bin(buf[CCR_MIN]);
101 tm->tm_hour = bcd2bin(buf[CCR_HOUR] & 0x3F); /* hr is 0-23 */
102 tm->tm_mday = bcd2bin(buf[CCR_MDAY]);
103 tm->tm_mon = bcd2bin(buf[CCR_MONTH]); /* mon is 0-11 */
104 tm->tm_year = bcd2bin(buf[CCR_YEAR])
105 + (bcd2bin(buf[CCR_Y2K]) * 100);
Stefan Roese5a44c602007-10-21 08:16:12 +0200106 tm->tm_wday = buf[CCR_WDAY];
107
108 debug("%s: tm is secs=%d, mins=%d, hours=%d, "
109 "mday=%d, mon=%d, year=%d, wday=%d\n",
110 __FUNCTION__,
111 tm->tm_sec, tm->tm_min, tm->tm_hour,
112 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
Yuri Tikhonov9bacd942008-03-20 17:56:04 +0300113
114 return 0;
Stefan Roese5a44c602007-10-21 08:16:12 +0200115}
116
Jean-Christophe PLAGNIOL-VILLARD97a2e102008-09-01 23:06:23 +0200117int rtc_set(struct rtc_time *tm)
Stefan Roese5a44c602007-10-21 08:16:12 +0200118{
119 int i;
120 u8 buf[8];
121
122 debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
123 tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
124 tm->tm_hour, tm->tm_min, tm->tm_sec);
125
Albin Tonnerre8aca7202009-08-13 15:31:11 +0200126 buf[CCR_SEC] = bin2bcd(tm->tm_sec);
127 buf[CCR_MIN] = bin2bcd(tm->tm_min);
Stefan Roese5a44c602007-10-21 08:16:12 +0200128
129 /* set hour and 24hr bit */
Albin Tonnerre8aca7202009-08-13 15:31:11 +0200130 buf[CCR_HOUR] = bin2bcd(tm->tm_hour) | X1205_HR_MIL;
Stefan Roese5a44c602007-10-21 08:16:12 +0200131
Albin Tonnerre8aca7202009-08-13 15:31:11 +0200132 buf[CCR_MDAY] = bin2bcd(tm->tm_mday);
Stefan Roese5a44c602007-10-21 08:16:12 +0200133
134 /* month, 1 - 12 */
Albin Tonnerre8aca7202009-08-13 15:31:11 +0200135 buf[CCR_MONTH] = bin2bcd(tm->tm_mon);
Stefan Roese5a44c602007-10-21 08:16:12 +0200136
137 /* year, since the rtc epoch*/
Albin Tonnerre8aca7202009-08-13 15:31:11 +0200138 buf[CCR_YEAR] = bin2bcd(tm->tm_year % 100);
Stefan Roese5a44c602007-10-21 08:16:12 +0200139 buf[CCR_WDAY] = tm->tm_wday & 0x07;
Albin Tonnerre8aca7202009-08-13 15:31:11 +0200140 buf[CCR_Y2K] = bin2bcd(tm->tm_year / 100);
Stefan Roese5a44c602007-10-21 08:16:12 +0200141
142 /* this sequence is required to unlock the chip */
143 rtc_write(X1205_REG_SR, X1205_SR_WEL);
144 rtc_write(X1205_REG_SR, X1205_SR_WEL | X1205_SR_RWEL);
145
146 /* write register's data */
147 for (i = 0; i < 8; i++)
148 rtc_write(X1205_CCR_BASE + i, buf[i]);
149
150 rtc_write(X1205_REG_SR, 0);
Jean-Christophe PLAGNIOL-VILLARD97a2e102008-09-01 23:06:23 +0200151
152 return 0;
Stefan Roese5a44c602007-10-21 08:16:12 +0200153}
154
155void rtc_reset(void)
156{
157 /*
158 * Nothing to do
159 */
160}