Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
Stefan Roese | ae6223d | 2015-01-19 11:33:40 +0100 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) Marvell International Ltd. and its affiliates |
Stefan Roese | ae6223d | 2015-01-19 11:33:40 +0100 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
| 7 | #include <i2c.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 8 | #include <log.h> |
Stefan Roese | ae6223d | 2015-01-19 11:33:40 +0100 | [diff] [blame] | 9 | #include <spl.h> |
| 10 | #include <asm/io.h> |
| 11 | #include <asm/arch/cpu.h> |
| 12 | #include <asm/arch/soc.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame^] | 13 | #include <linux/delay.h> |
Stefan Roese | ae6223d | 2015-01-19 11:33:40 +0100 | [diff] [blame] | 14 | |
| 15 | #include "ddr3_init.h" |
| 16 | |
| 17 | #if defined(MV88F78X60) |
| 18 | #include "ddr3_axp_vars.h" |
| 19 | #elif defined(MV88F67XX) |
| 20 | #include "ddr3_a370_vars.h" |
| 21 | #elif defined(MV88F672X) |
| 22 | #include "ddr3_a375_vars.h" |
| 23 | #endif |
| 24 | |
| 25 | #ifdef STATIC_TRAINING |
| 26 | static void ddr3_static_training_init(void); |
| 27 | #endif |
| 28 | #ifdef DUNIT_STATIC |
| 29 | static void ddr3_static_mc_init(void); |
| 30 | #endif |
| 31 | #if defined(DUNIT_STATIC) || defined(STATIC_TRAINING) |
| 32 | MV_DRAM_MODES *ddr3_get_static_ddr_mode(void); |
| 33 | #endif |
| 34 | #if defined(MV88F672X) |
| 35 | void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps); |
| 36 | #endif |
| 37 | u32 mv_board_id_get(void); |
| 38 | extern void ddr3_set_sw_wl_rl_debug(u32); |
| 39 | extern void ddr3_set_pbs(u32); |
| 40 | extern void ddr3_set_log_level(u32 val); |
| 41 | |
| 42 | static u32 log_level = DDR3_LOG_LEVEL; |
| 43 | |
| 44 | static u32 ddr3_init_main(void); |
| 45 | |
| 46 | /* |
| 47 | * Name: ddr3_set_log_level |
| 48 | * Desc: This routine initialize the log_level acording to nLogLevel |
| 49 | * which getting from user |
| 50 | * Args: nLogLevel |
| 51 | * Notes: |
| 52 | * Returns: None. |
| 53 | */ |
| 54 | void ddr3_set_log_level(u32 val) |
| 55 | { |
| 56 | log_level = val; |
| 57 | } |
| 58 | |
| 59 | /* |
| 60 | * Name: ddr3_get_log_level |
| 61 | * Desc: This routine returns the log level |
| 62 | * Args: none |
| 63 | * Notes: |
| 64 | * Returns: log level. |
| 65 | */ |
| 66 | u32 ddr3_get_log_level(void) |
| 67 | { |
| 68 | return log_level; |
| 69 | } |
| 70 | |
| 71 | static void debug_print_reg(u32 reg) |
| 72 | { |
| 73 | printf("0x%08x = 0x%08x\n", reg, reg_read(reg)); |
| 74 | } |
| 75 | |
| 76 | static void print_dunit_setup(void) |
| 77 | { |
| 78 | puts("\n########### LOG LEVEL 1 (D-UNIT SETUP)###########\n"); |
| 79 | |
| 80 | #ifdef DUNIT_STATIC |
| 81 | puts("\nStatic D-UNIT Setup:\n"); |
| 82 | #endif |
| 83 | #ifdef DUNIT_SPD |
| 84 | puts("\nDynamic(using SPD) D-UNIT Setup:\n"); |
| 85 | #endif |
| 86 | debug_print_reg(REG_SDRAM_CONFIG_ADDR); |
| 87 | debug_print_reg(REG_DUNIT_CTRL_LOW_ADDR); |
| 88 | debug_print_reg(REG_SDRAM_TIMING_LOW_ADDR); |
| 89 | debug_print_reg(REG_SDRAM_TIMING_HIGH_ADDR); |
| 90 | debug_print_reg(REG_SDRAM_ADDRESS_CTRL_ADDR); |
| 91 | debug_print_reg(REG_SDRAM_OPEN_PAGES_ADDR); |
| 92 | debug_print_reg(REG_SDRAM_OPERATION_ADDR); |
| 93 | debug_print_reg(REG_SDRAM_MODE_ADDR); |
| 94 | debug_print_reg(REG_SDRAM_EXT_MODE_ADDR); |
| 95 | debug_print_reg(REG_DDR_CONT_HIGH_ADDR); |
| 96 | debug_print_reg(REG_ODT_TIME_LOW_ADDR); |
| 97 | debug_print_reg(REG_SDRAM_ERROR_ADDR); |
| 98 | debug_print_reg(REG_SDRAM_AUTO_PWR_SAVE_ADDR); |
| 99 | debug_print_reg(REG_OUDDR3_TIMING_ADDR); |
| 100 | debug_print_reg(REG_ODT_TIME_HIGH_ADDR); |
| 101 | debug_print_reg(REG_SDRAM_ODT_CTRL_LOW_ADDR); |
| 102 | debug_print_reg(REG_SDRAM_ODT_CTRL_HIGH_ADDR); |
| 103 | debug_print_reg(REG_DUNIT_ODT_CTRL_ADDR); |
| 104 | #ifndef MV88F67XX |
| 105 | debug_print_reg(REG_DRAM_FIFO_CTRL_ADDR); |
| 106 | debug_print_reg(REG_DRAM_AXI_CTRL_ADDR); |
| 107 | debug_print_reg(REG_DRAM_ADDR_CTRL_DRIVE_STRENGTH_ADDR); |
| 108 | debug_print_reg(REG_DRAM_DATA_DQS_DRIVE_STRENGTH_ADDR); |
| 109 | debug_print_reg(REG_DRAM_VER_CAL_MACHINE_CTRL_ADDR); |
| 110 | debug_print_reg(REG_DRAM_MAIN_PADS_CAL_ADDR); |
| 111 | debug_print_reg(REG_DRAM_HOR_CAL_MACHINE_CTRL_ADDR); |
| 112 | debug_print_reg(REG_CS_SIZE_SCRATCH_ADDR); |
| 113 | debug_print_reg(REG_DYNAMIC_POWER_SAVE_ADDR); |
| 114 | debug_print_reg(REG_READ_DATA_SAMPLE_DELAYS_ADDR); |
| 115 | debug_print_reg(REG_READ_DATA_READY_DELAYS_ADDR); |
| 116 | debug_print_reg(REG_DDR3_MR0_ADDR); |
| 117 | debug_print_reg(REG_DDR3_MR1_ADDR); |
| 118 | debug_print_reg(REG_DDR3_MR2_ADDR); |
| 119 | debug_print_reg(REG_DDR3_MR3_ADDR); |
| 120 | debug_print_reg(REG_DDR3_RANK_CTRL_ADDR); |
| 121 | debug_print_reg(REG_DRAM_PHY_CONFIG_ADDR); |
| 122 | debug_print_reg(REG_STATIC_DRAM_DLB_CONTROL); |
| 123 | debug_print_reg(DLB_BUS_OPTIMIZATION_WEIGHTS_REG); |
| 124 | debug_print_reg(DLB_AGING_REGISTER); |
| 125 | debug_print_reg(DLB_EVICTION_CONTROL_REG); |
| 126 | debug_print_reg(DLB_EVICTION_TIMERS_REGISTER_REG); |
| 127 | #if defined(MV88F672X) |
| 128 | debug_print_reg(REG_FASTPATH_WIN_CTRL_ADDR(0)); |
| 129 | debug_print_reg(REG_FASTPATH_WIN_BASE_ADDR(0)); |
| 130 | debug_print_reg(REG_FASTPATH_WIN_CTRL_ADDR(1)); |
| 131 | debug_print_reg(REG_FASTPATH_WIN_BASE_ADDR(1)); |
| 132 | #else |
| 133 | debug_print_reg(REG_FASTPATH_WIN_0_CTRL_ADDR); |
| 134 | #endif |
| 135 | debug_print_reg(REG_CDI_CONFIG_ADDR); |
| 136 | #endif |
| 137 | } |
| 138 | |
| 139 | #if !defined(STATIC_TRAINING) |
| 140 | static void ddr3_restore_and_set_final_windows(u32 *win_backup) |
| 141 | { |
| 142 | u32 ui, reg, cs; |
| 143 | u32 win_ctrl_reg, num_of_win_regs; |
| 144 | u32 cs_ena = ddr3_get_cs_ena_from_reg(); |
| 145 | |
| 146 | #if defined(MV88F672X) |
| 147 | if (DDR3_FAST_PATH_EN == 0) |
| 148 | return; |
| 149 | #endif |
| 150 | |
| 151 | #if defined(MV88F672X) |
| 152 | win_ctrl_reg = REG_XBAR_WIN_16_CTRL_ADDR; |
| 153 | num_of_win_regs = 8; |
| 154 | #else |
| 155 | win_ctrl_reg = REG_XBAR_WIN_4_CTRL_ADDR; |
| 156 | num_of_win_regs = 16; |
| 157 | #endif |
| 158 | |
| 159 | /* Return XBAR windows 4-7 or 16-19 init configuration */ |
| 160 | for (ui = 0; ui < num_of_win_regs; ui++) |
| 161 | reg_write((win_ctrl_reg + 0x4 * ui), win_backup[ui]); |
| 162 | |
| 163 | DEBUG_INIT_FULL_S("DDR3 Training Sequence - Switching XBAR Window to FastPath Window\n"); |
| 164 | |
| 165 | #if defined(MV88F672X) |
| 166 | /* Set L2 filtering to 1G */ |
| 167 | reg_write(0x8c04, 0x40000000); |
| 168 | |
| 169 | /* Open fast path windows */ |
| 170 | for (cs = 0; cs < MAX_CS; cs++) { |
| 171 | if (cs_ena & (1 << cs)) { |
| 172 | /* set fast path window control for the cs */ |
| 173 | reg = 0x1FFFFFE1; |
| 174 | reg |= (cs << 2); |
| 175 | reg |= (SDRAM_CS_SIZE & 0xFFFF0000); |
| 176 | /* Open fast path Window */ |
| 177 | reg_write(REG_FASTPATH_WIN_CTRL_ADDR(cs), reg); |
| 178 | /* set fast path window base address for the cs */ |
| 179 | reg = (((SDRAM_CS_SIZE + 1) * cs) & 0xFFFF0000); |
| 180 | /* Set base address */ |
| 181 | reg_write(REG_FASTPATH_WIN_BASE_ADDR(cs), reg); |
| 182 | } |
| 183 | } |
| 184 | #else |
| 185 | reg = 0x1FFFFFE1; |
| 186 | for (cs = 0; cs < MAX_CS; cs++) { |
| 187 | if (cs_ena & (1 << cs)) { |
| 188 | reg |= (cs << 2); |
| 189 | break; |
| 190 | } |
| 191 | } |
| 192 | |
| 193 | /* Open fast path Window to - 0.5G */ |
| 194 | reg_write(REG_FASTPATH_WIN_0_CTRL_ADDR, reg); |
| 195 | #endif |
| 196 | } |
| 197 | |
| 198 | static void ddr3_save_and_set_training_windows(u32 *win_backup) |
| 199 | { |
| 200 | u32 cs_ena = ddr3_get_cs_ena_from_reg(); |
| 201 | u32 reg, tmp_count, cs, ui; |
| 202 | u32 win_ctrl_reg, win_base_reg, win_remap_reg; |
| 203 | u32 num_of_win_regs, win_jump_index; |
| 204 | |
| 205 | #if defined(MV88F672X) |
| 206 | /* Disable L2 filtering */ |
| 207 | reg_write(0x8c04, 0); |
| 208 | |
| 209 | win_ctrl_reg = REG_XBAR_WIN_16_CTRL_ADDR; |
| 210 | win_base_reg = REG_XBAR_WIN_16_BASE_ADDR; |
| 211 | win_remap_reg = REG_XBAR_WIN_16_REMAP_ADDR; |
| 212 | win_jump_index = 0x8; |
| 213 | num_of_win_regs = 8; |
| 214 | #else |
| 215 | win_ctrl_reg = REG_XBAR_WIN_4_CTRL_ADDR; |
| 216 | win_base_reg = REG_XBAR_WIN_4_BASE_ADDR; |
| 217 | win_remap_reg = REG_XBAR_WIN_4_REMAP_ADDR; |
| 218 | win_jump_index = 0x10; |
| 219 | num_of_win_regs = 16; |
| 220 | #endif |
| 221 | |
| 222 | /* Close XBAR Window 19 - Not needed */ |
| 223 | /* {0x000200e8} - Open Mbus Window - 2G */ |
| 224 | reg_write(REG_XBAR_WIN_19_CTRL_ADDR, 0); |
| 225 | |
| 226 | /* Save XBAR Windows 4-19 init configurations */ |
| 227 | for (ui = 0; ui < num_of_win_regs; ui++) |
| 228 | win_backup[ui] = reg_read(win_ctrl_reg + 0x4 * ui); |
| 229 | |
| 230 | /* Open XBAR Windows 4-7 or 16-19 for other CS */ |
| 231 | reg = 0; |
| 232 | tmp_count = 0; |
| 233 | for (cs = 0; cs < MAX_CS; cs++) { |
| 234 | if (cs_ena & (1 << cs)) { |
| 235 | switch (cs) { |
| 236 | case 0: |
| 237 | reg = 0x0E00; |
| 238 | break; |
| 239 | case 1: |
| 240 | reg = 0x0D00; |
| 241 | break; |
| 242 | case 2: |
| 243 | reg = 0x0B00; |
| 244 | break; |
| 245 | case 3: |
| 246 | reg = 0x0700; |
| 247 | break; |
| 248 | } |
| 249 | reg |= (1 << 0); |
| 250 | reg |= (SDRAM_CS_SIZE & 0xFFFF0000); |
| 251 | |
| 252 | reg_write(win_ctrl_reg + win_jump_index * tmp_count, |
| 253 | reg); |
| 254 | reg = ((SDRAM_CS_SIZE + 1) * (tmp_count)) & 0xFFFF0000; |
| 255 | reg_write(win_base_reg + win_jump_index * tmp_count, |
| 256 | reg); |
| 257 | |
| 258 | if (win_remap_reg <= REG_XBAR_WIN_7_REMAP_ADDR) { |
| 259 | reg_write(win_remap_reg + |
| 260 | win_jump_index * tmp_count, 0); |
| 261 | } |
| 262 | |
| 263 | tmp_count++; |
| 264 | } |
| 265 | } |
| 266 | } |
| 267 | #endif /* !defined(STATIC_TRAINING) */ |
| 268 | |
| 269 | /* |
| 270 | * Name: ddr3_init - Main DDR3 Init function |
| 271 | * Desc: This routine initialize the DDR3 MC and runs HW training. |
| 272 | * Args: None. |
| 273 | * Notes: |
| 274 | * Returns: None. |
| 275 | */ |
| 276 | int ddr3_init(void) |
| 277 | { |
| 278 | unsigned int status; |
| 279 | |
| 280 | ddr3_set_pbs(DDR3_PBS); |
| 281 | ddr3_set_sw_wl_rl_debug(DDR3_RUN_SW_WHEN_HW_FAIL); |
| 282 | |
| 283 | status = ddr3_init_main(); |
| 284 | if (status == MV_DDR3_TRAINING_ERR_BAD_SAR) |
| 285 | DEBUG_INIT_S("DDR3 Training Error: Bad sample at reset"); |
| 286 | if (status == MV_DDR3_TRAINING_ERR_BAD_DIMM_SETUP) |
| 287 | DEBUG_INIT_S("DDR3 Training Error: Bad DIMM setup"); |
| 288 | if (status == MV_DDR3_TRAINING_ERR_MAX_CS_LIMIT) |
| 289 | DEBUG_INIT_S("DDR3 Training Error: Max CS limit"); |
| 290 | if (status == MV_DDR3_TRAINING_ERR_MAX_ENA_CS_LIMIT) |
| 291 | DEBUG_INIT_S("DDR3 Training Error: Max enable CS limit"); |
| 292 | if (status == MV_DDR3_TRAINING_ERR_BAD_R_DIMM_SETUP) |
| 293 | DEBUG_INIT_S("DDR3 Training Error: Bad R-DIMM setup"); |
| 294 | if (status == MV_DDR3_TRAINING_ERR_TWSI_FAIL) |
| 295 | DEBUG_INIT_S("DDR3 Training Error: TWSI failure"); |
| 296 | if (status == MV_DDR3_TRAINING_ERR_DIMM_TYPE_NO_MATCH) |
| 297 | DEBUG_INIT_S("DDR3 Training Error: DIMM type no match"); |
| 298 | if (status == MV_DDR3_TRAINING_ERR_TWSI_BAD_TYPE) |
| 299 | DEBUG_INIT_S("DDR3 Training Error: TWSI bad type"); |
| 300 | if (status == MV_DDR3_TRAINING_ERR_BUS_WIDTH_NOT_MATCH) |
| 301 | DEBUG_INIT_S("DDR3 Training Error: bus width no match"); |
| 302 | if (status > MV_DDR3_TRAINING_ERR_HW_FAIL_BASE) |
| 303 | DEBUG_INIT_C("DDR3 Training Error: HW Failure 0x", status, 8); |
| 304 | |
| 305 | return status; |
| 306 | } |
| 307 | |
| 308 | static void print_ddr_target_freq(u32 cpu_freq, u32 fab_opt) |
| 309 | { |
| 310 | puts("\nDDR3 Training Sequence - Run DDR3 at "); |
| 311 | |
| 312 | switch (cpu_freq) { |
| 313 | #if defined(MV88F672X) |
| 314 | case 21: |
| 315 | puts("533 Mhz\n"); |
| 316 | break; |
| 317 | #else |
| 318 | case 1: |
| 319 | puts("533 Mhz\n"); |
| 320 | break; |
| 321 | case 2: |
| 322 | if (fab_opt == 5) |
| 323 | puts("600 Mhz\n"); |
| 324 | if (fab_opt == 9) |
| 325 | puts("400 Mhz\n"); |
| 326 | break; |
| 327 | case 3: |
| 328 | puts("667 Mhz\n"); |
| 329 | break; |
| 330 | case 4: |
| 331 | if (fab_opt == 5) |
| 332 | puts("750 Mhz\n"); |
| 333 | if (fab_opt == 9) |
| 334 | puts("500 Mhz\n"); |
| 335 | break; |
| 336 | case 0xa: |
| 337 | puts("400 Mhz\n"); |
| 338 | break; |
| 339 | case 0xb: |
| 340 | if (fab_opt == 5) |
| 341 | puts("800 Mhz\n"); |
| 342 | if (fab_opt == 9) |
| 343 | puts("553 Mhz\n"); |
| 344 | if (fab_opt == 0xA) |
| 345 | puts("640 Mhz\n"); |
| 346 | break; |
| 347 | #endif |
| 348 | default: |
| 349 | puts("NOT DEFINED FREQ\n"); |
| 350 | } |
| 351 | } |
| 352 | |
| 353 | static u32 ddr3_init_main(void) |
| 354 | { |
| 355 | u32 target_freq; |
| 356 | u32 reg = 0; |
| 357 | u32 cpu_freq, fab_opt, hclk_time_ps, soc_num; |
| 358 | __maybe_unused u32 ecc = DRAM_ECC; |
| 359 | __maybe_unused int dqs_clk_aligned = 0; |
| 360 | __maybe_unused u32 scrub_offs, scrub_size; |
| 361 | __maybe_unused u32 ddr_width = BUS_WIDTH; |
| 362 | __maybe_unused int status; |
| 363 | __maybe_unused u32 win_backup[16]; |
| 364 | |
| 365 | /* SoC/Board special Initializtions */ |
| 366 | fab_opt = ddr3_get_fab_opt(); |
| 367 | |
| 368 | #ifdef CONFIG_SPD_EEPROM |
| 369 | i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); |
| 370 | #endif |
| 371 | |
| 372 | ddr3_print_version(); |
| 373 | DEBUG_INIT_S("4\n"); |
| 374 | /* Lib version 5.5.4 */ |
| 375 | |
| 376 | fab_opt = ddr3_get_fab_opt(); |
| 377 | |
| 378 | /* Switching CPU to MRVL ID */ |
| 379 | soc_num = (reg_read(REG_SAMPLE_RESET_HIGH_ADDR) & SAR1_CPU_CORE_MASK) >> |
| 380 | SAR1_CPU_CORE_OFFSET; |
| 381 | switch (soc_num) { |
| 382 | case 0x3: |
| 383 | reg_bit_set(CPU_CONFIGURATION_REG(3), CPU_MRVL_ID_OFFSET); |
| 384 | reg_bit_set(CPU_CONFIGURATION_REG(2), CPU_MRVL_ID_OFFSET); |
| 385 | case 0x1: |
| 386 | reg_bit_set(CPU_CONFIGURATION_REG(1), CPU_MRVL_ID_OFFSET); |
| 387 | case 0x0: |
| 388 | reg_bit_set(CPU_CONFIGURATION_REG(0), CPU_MRVL_ID_OFFSET); |
| 389 | default: |
| 390 | break; |
| 391 | } |
| 392 | |
| 393 | /* Power down deskew PLL */ |
| 394 | #if !defined(MV88F672X) |
| 395 | /* 0x18780 [25] */ |
| 396 | reg = (reg_read(REG_DDRPHY_APLL_CTRL_ADDR) & ~(1 << 25)); |
| 397 | reg_write(REG_DDRPHY_APLL_CTRL_ADDR, reg); |
| 398 | #endif |
| 399 | |
| 400 | /* |
| 401 | * Stage 0 - Set board configuration |
| 402 | */ |
| 403 | cpu_freq = ddr3_get_cpu_freq(); |
| 404 | if (fab_opt > FAB_OPT) |
| 405 | fab_opt = FAB_OPT - 1; |
| 406 | |
| 407 | if (ddr3_get_log_level() > 0) |
| 408 | print_ddr_target_freq(cpu_freq, fab_opt); |
| 409 | |
| 410 | #if defined(MV88F672X) |
| 411 | get_target_freq(cpu_freq, &target_freq, &hclk_time_ps); |
| 412 | #else |
| 413 | target_freq = cpu_ddr_ratios[fab_opt][cpu_freq]; |
| 414 | hclk_time_ps = cpu_fab_clk_to_hclk[fab_opt][cpu_freq]; |
| 415 | #endif |
| 416 | if ((target_freq == 0) || (hclk_time_ps == 0)) { |
| 417 | DEBUG_INIT_S("DDR3 Training Sequence - FAILED - Wrong Sample at Reset Configurations\n"); |
| 418 | if (target_freq == 0) { |
| 419 | DEBUG_INIT_C("target_freq", target_freq, 2); |
| 420 | DEBUG_INIT_C("fab_opt", fab_opt, 2); |
| 421 | DEBUG_INIT_C("cpu_freq", cpu_freq, 2); |
| 422 | } else if (hclk_time_ps == 0) { |
| 423 | DEBUG_INIT_C("hclk_time_ps", hclk_time_ps, 2); |
| 424 | DEBUG_INIT_C("fab_opt", fab_opt, 2); |
| 425 | DEBUG_INIT_C("cpu_freq", cpu_freq, 2); |
| 426 | } |
| 427 | |
| 428 | return MV_DDR3_TRAINING_ERR_BAD_SAR; |
| 429 | } |
| 430 | |
| 431 | #if defined(ECC_SUPPORT) |
| 432 | scrub_offs = U_BOOT_START_ADDR; |
| 433 | scrub_size = U_BOOT_SCRUB_SIZE; |
| 434 | #else |
| 435 | scrub_offs = 0; |
| 436 | scrub_size = 0; |
| 437 | #endif |
| 438 | |
| 439 | #if defined(ECC_SUPPORT) && defined(AUTO_DETECTION_SUPPORT) |
Stefan Roese | ae6223d | 2015-01-19 11:33:40 +0100 | [diff] [blame] | 440 | ecc = 0; |
| 441 | if (ddr3_check_config(BUS_WIDTH_ECC_TWSI_ADDR, CONFIG_ECC)) |
| 442 | ecc = 1; |
| 443 | #endif |
| 444 | |
| 445 | #ifdef DQS_CLK_ALIGNED |
| 446 | dqs_clk_aligned = 1; |
| 447 | #endif |
| 448 | |
| 449 | /* Check if DRAM is already initialized */ |
| 450 | if (reg_read(REG_BOOTROM_ROUTINE_ADDR) & |
| 451 | (1 << REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS)) { |
| 452 | DEBUG_INIT_S("DDR3 Training Sequence - 2nd boot - Skip\n"); |
| 453 | return MV_OK; |
| 454 | } |
| 455 | |
| 456 | /* |
| 457 | * Stage 1 - Dunit Setup |
| 458 | */ |
| 459 | |
| 460 | #ifdef DUNIT_STATIC |
| 461 | /* |
| 462 | * For Static D-Unit Setup use must set the correct static values |
| 463 | * at the ddr3_*soc*_vars.h file |
| 464 | */ |
| 465 | DEBUG_INIT_FULL_S("DDR3 Training Sequence - Static MC Init\n"); |
| 466 | ddr3_static_mc_init(); |
| 467 | |
| 468 | #ifdef ECC_SUPPORT |
| 469 | ecc = DRAM_ECC; |
| 470 | if (ecc) { |
| 471 | reg = reg_read(REG_SDRAM_CONFIG_ADDR); |
| 472 | reg |= (1 << REG_SDRAM_CONFIG_ECC_OFFS); |
| 473 | reg_write(REG_SDRAM_CONFIG_ADDR, reg); |
| 474 | } |
| 475 | #endif |
| 476 | #endif |
| 477 | |
| 478 | #if defined(MV88F78X60) || defined(MV88F672X) |
| 479 | #if defined(AUTO_DETECTION_SUPPORT) |
| 480 | /* |
| 481 | * Configurations for both static and dynamic MC setups |
| 482 | * |
| 483 | * Dynamically Set 32Bit and ECC for AXP (Relevant only for |
| 484 | * Marvell DB boards) |
| 485 | */ |
| 486 | if (ddr3_check_config(BUS_WIDTH_ECC_TWSI_ADDR, CONFIG_BUS_WIDTH)) { |
| 487 | ddr_width = 32; |
| 488 | DEBUG_INIT_S("DDR3 Training Sequence - DRAM bus width 32Bit\n"); |
| 489 | } |
| 490 | #endif |
| 491 | |
| 492 | #if defined(MV88F672X) |
| 493 | reg = reg_read(REG_SDRAM_CONFIG_ADDR); |
| 494 | if ((reg >> 15) & 1) |
| 495 | ddr_width = 32; |
| 496 | else |
| 497 | ddr_width = 16; |
| 498 | #endif |
| 499 | #endif |
| 500 | |
| 501 | #ifdef DUNIT_SPD |
| 502 | status = ddr3_dunit_setup(ecc, hclk_time_ps, &ddr_width); |
| 503 | if (MV_OK != status) { |
| 504 | DEBUG_INIT_S("DDR3 Training Sequence - FAILED (ddr3 Dunit Setup)\n"); |
| 505 | return status; |
| 506 | } |
| 507 | #endif |
| 508 | |
| 509 | /* Fix read ready phases for all SOC in reg 0x15C8 */ |
| 510 | reg = reg_read(REG_TRAINING_DEBUG_3_ADDR); |
| 511 | reg &= ~(REG_TRAINING_DEBUG_3_MASK); |
| 512 | reg |= 0x4; /* Phase 0 */ |
| 513 | reg &= ~(REG_TRAINING_DEBUG_3_MASK << REG_TRAINING_DEBUG_3_OFFS); |
| 514 | reg |= (0x4 << (1 * REG_TRAINING_DEBUG_3_OFFS)); /* Phase 1 */ |
| 515 | reg &= ~(REG_TRAINING_DEBUG_3_MASK << (3 * REG_TRAINING_DEBUG_3_OFFS)); |
| 516 | reg |= (0x6 << (3 * REG_TRAINING_DEBUG_3_OFFS)); /* Phase 3 */ |
| 517 | reg &= ~(REG_TRAINING_DEBUG_3_MASK << (4 * REG_TRAINING_DEBUG_3_OFFS)); |
| 518 | reg |= (0x6 << (4 * REG_TRAINING_DEBUG_3_OFFS)); |
| 519 | reg &= ~(REG_TRAINING_DEBUG_3_MASK << (5 * REG_TRAINING_DEBUG_3_OFFS)); |
| 520 | reg |= (0x6 << (5 * REG_TRAINING_DEBUG_3_OFFS)); |
| 521 | reg_write(REG_TRAINING_DEBUG_3_ADDR, reg); |
| 522 | |
| 523 | #if defined(MV88F672X) |
| 524 | /* |
| 525 | * AxiBrespMode[8] = Compliant, |
| 526 | * AxiAddrDecodeCntrl[11] = Internal, |
| 527 | * AxiDataBusWidth[0] = 128bit |
| 528 | */ |
| 529 | /* 0x14A8 - AXI Control Register */ |
| 530 | reg_write(REG_DRAM_AXI_CTRL_ADDR, 0); |
| 531 | #else |
| 532 | /* 0x14A8 - AXI Control Register */ |
| 533 | reg_write(REG_DRAM_AXI_CTRL_ADDR, 0x00000100); |
| 534 | reg_write(REG_CDI_CONFIG_ADDR, 0x00000006); |
| 535 | |
| 536 | if ((ddr_width == 64) && (reg_read(REG_DDR_IO_ADDR) & |
| 537 | (1 << REG_DDR_IO_CLK_RATIO_OFFS))) { |
| 538 | /* 0x14A8 - AXI Control Register */ |
| 539 | reg_write(REG_DRAM_AXI_CTRL_ADDR, 0x00000101); |
| 540 | reg_write(REG_CDI_CONFIG_ADDR, 0x00000007); |
| 541 | } |
| 542 | #endif |
| 543 | |
| 544 | #if !defined(MV88F67XX) |
| 545 | /* |
| 546 | * ARMADA-370 activate DLB later at the u-boot, |
| 547 | * Armada38x - No DLB activation at this time |
| 548 | */ |
| 549 | reg_write(DLB_BUS_OPTIMIZATION_WEIGHTS_REG, 0x18C01E); |
| 550 | |
| 551 | #if defined(MV88F78X60) |
| 552 | /* WA according to eratta GL-8672902*/ |
| 553 | if (mv_ctrl_rev_get() == MV_78XX0_B0_REV) |
| 554 | reg_write(DLB_BUS_OPTIMIZATION_WEIGHTS_REG, 0xc19e); |
| 555 | #endif |
| 556 | |
| 557 | reg_write(DLB_AGING_REGISTER, 0x0f7f007f); |
| 558 | reg_write(DLB_EVICTION_CONTROL_REG, 0x0); |
| 559 | reg_write(DLB_EVICTION_TIMERS_REGISTER_REG, 0x00FF3C1F); |
| 560 | |
| 561 | reg_write(MBUS_UNITS_PRIORITY_CONTROL_REG, 0x55555555); |
| 562 | reg_write(FABRIC_UNITS_PRIORITY_CONTROL_REG, 0xAA); |
| 563 | reg_write(MBUS_UNITS_PREFETCH_CONTROL_REG, 0xffff); |
| 564 | reg_write(FABRIC_UNITS_PREFETCH_CONTROL_REG, 0xf0f); |
| 565 | |
| 566 | #if defined(MV88F78X60) |
| 567 | /* WA according to eratta GL-8672902 */ |
| 568 | if (mv_ctrl_rev_get() == MV_78XX0_B0_REV) { |
| 569 | reg = reg_read(REG_STATIC_DRAM_DLB_CONTROL); |
| 570 | reg |= DLB_ENABLE; |
| 571 | reg_write(REG_STATIC_DRAM_DLB_CONTROL, reg); |
| 572 | } |
| 573 | #endif /* end defined(MV88F78X60) */ |
| 574 | #endif /* end !defined(MV88F67XX) */ |
| 575 | |
| 576 | if (ddr3_get_log_level() >= MV_LOG_LEVEL_1) |
| 577 | print_dunit_setup(); |
| 578 | |
| 579 | /* |
| 580 | * Stage 2 - Training Values Setup |
| 581 | */ |
| 582 | #ifdef STATIC_TRAINING |
| 583 | /* |
| 584 | * DRAM Init - After all the D-unit values are set, its time to init |
| 585 | * the D-unit |
| 586 | */ |
| 587 | /* Wait for '0' */ |
| 588 | reg_write(REG_SDRAM_INIT_CTRL_ADDR, 0x1); |
| 589 | do { |
| 590 | reg = (reg_read(REG_SDRAM_INIT_CTRL_ADDR)) & |
| 591 | (1 << REG_SDRAM_INIT_CTRL_OFFS); |
| 592 | } while (reg); |
| 593 | |
| 594 | /* ddr3 init using static parameters - HW training is disabled */ |
| 595 | DEBUG_INIT_FULL_S("DDR3 Training Sequence - Static Training Parameters\n"); |
| 596 | ddr3_static_training_init(); |
| 597 | |
| 598 | #if defined(MV88F78X60) |
| 599 | /* |
| 600 | * If ECC is enabled, need to scrub the U-Boot area memory region - |
| 601 | * Run training function with Xor bypass just to scrub the memory |
| 602 | */ |
| 603 | status = ddr3_hw_training(target_freq, ddr_width, |
| 604 | 1, scrub_offs, scrub_size, |
| 605 | dqs_clk_aligned, DDR3_TRAINING_DEBUG, |
| 606 | REG_DIMM_SKIP_WL); |
| 607 | if (MV_OK != status) { |
| 608 | DEBUG_INIT_FULL_S("DDR3 Training Sequence - FAILED\n"); |
| 609 | return status; |
| 610 | } |
| 611 | #endif |
| 612 | #else |
| 613 | /* Set X-BAR windows for the training sequence */ |
| 614 | ddr3_save_and_set_training_windows(win_backup); |
| 615 | |
| 616 | /* Run DDR3 Training Sequence */ |
| 617 | /* DRAM Init */ |
| 618 | reg_write(REG_SDRAM_INIT_CTRL_ADDR, 0x1); |
| 619 | do { |
| 620 | reg = (reg_read(REG_SDRAM_INIT_CTRL_ADDR)) & |
| 621 | (1 << REG_SDRAM_INIT_CTRL_OFFS); |
| 622 | } while (reg); /* Wait for '0' */ |
| 623 | |
| 624 | /* ddr3 init using DDR3 HW training procedure */ |
| 625 | DEBUG_INIT_FULL_S("DDR3 Training Sequence - HW Training Procedure\n"); |
| 626 | status = ddr3_hw_training(target_freq, ddr_width, |
| 627 | 0, scrub_offs, scrub_size, |
| 628 | dqs_clk_aligned, DDR3_TRAINING_DEBUG, |
| 629 | REG_DIMM_SKIP_WL); |
| 630 | if (MV_OK != status) { |
| 631 | DEBUG_INIT_FULL_S("DDR3 Training Sequence - FAILED\n"); |
| 632 | return status; |
| 633 | } |
| 634 | #endif |
| 635 | |
| 636 | /* |
| 637 | * Stage 3 - Finish |
| 638 | */ |
| 639 | #if defined(MV88F78X60) || defined(MV88F672X) |
| 640 | /* Disable ECC Ignore bit */ |
| 641 | reg = reg_read(REG_SDRAM_CONFIG_ADDR) & |
| 642 | ~(1 << REG_SDRAM_CONFIG_IERR_OFFS); |
| 643 | reg_write(REG_SDRAM_CONFIG_ADDR, reg); |
| 644 | #endif |
| 645 | |
| 646 | #if !defined(STATIC_TRAINING) |
| 647 | /* Restore and set windows */ |
| 648 | ddr3_restore_and_set_final_windows(win_backup); |
| 649 | #endif |
| 650 | |
| 651 | /* Update DRAM init indication in bootROM register */ |
| 652 | reg = reg_read(REG_BOOTROM_ROUTINE_ADDR); |
| 653 | reg_write(REG_BOOTROM_ROUTINE_ADDR, |
| 654 | reg | (1 << REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS)); |
| 655 | |
| 656 | #if !defined(MV88F67XX) |
| 657 | #if defined(MV88F78X60) |
| 658 | if (mv_ctrl_rev_get() == MV_78XX0_B0_REV) { |
| 659 | reg = reg_read(REG_SDRAM_CONFIG_ADDR); |
| 660 | if (ecc == 0) |
| 661 | reg_write(REG_SDRAM_CONFIG_ADDR, reg | (1 << 19)); |
| 662 | } |
| 663 | #endif /* end defined(MV88F78X60) */ |
| 664 | |
| 665 | reg_write(DLB_EVICTION_CONTROL_REG, 0x9); |
| 666 | |
| 667 | reg = reg_read(REG_STATIC_DRAM_DLB_CONTROL); |
| 668 | reg |= (DLB_ENABLE | DLB_WRITE_COALESING | DLB_AXI_PREFETCH_EN | |
| 669 | DLB_MBUS_PREFETCH_EN | PREFETCH_NLNSZTR); |
| 670 | reg_write(REG_STATIC_DRAM_DLB_CONTROL, reg); |
| 671 | #endif /* end !defined(MV88F67XX) */ |
| 672 | |
| 673 | #ifdef STATIC_TRAINING |
| 674 | DEBUG_INIT_S("DDR3 Training Sequence - Ended Successfully (S)\n"); |
| 675 | #else |
| 676 | DEBUG_INIT_S("DDR3 Training Sequence - Ended Successfully\n"); |
| 677 | #endif |
| 678 | |
| 679 | return MV_OK; |
| 680 | } |
| 681 | |
| 682 | /* |
| 683 | * Name: ddr3_get_cpu_freq |
| 684 | * Desc: read S@R and return CPU frequency |
| 685 | * Args: |
| 686 | * Notes: |
| 687 | * Returns: required value |
| 688 | */ |
| 689 | |
| 690 | u32 ddr3_get_cpu_freq(void) |
| 691 | { |
| 692 | u32 reg, cpu_freq; |
| 693 | |
| 694 | #if defined(MV88F672X) |
| 695 | /* Read sample at reset setting */ |
| 696 | reg = reg_read(REG_SAMPLE_RESET_HIGH_ADDR); /* 0xE8200 */ |
| 697 | cpu_freq = (reg & REG_SAMPLE_RESET_CPU_FREQ_MASK) >> |
| 698 | REG_SAMPLE_RESET_CPU_FREQ_OFFS; |
| 699 | #else |
| 700 | /* Read sample at reset setting */ |
| 701 | reg = reg_read(REG_SAMPLE_RESET_LOW_ADDR); /* 0x18230 [23:21] */ |
| 702 | #if defined(MV88F78X60) |
| 703 | cpu_freq = (reg & REG_SAMPLE_RESET_CPU_FREQ_MASK) >> |
| 704 | REG_SAMPLE_RESET_CPU_FREQ_OFFS; |
| 705 | reg = reg_read(REG_SAMPLE_RESET_HIGH_ADDR); /* 0x18234 [20] */ |
| 706 | cpu_freq |= (((reg >> REG_SAMPLE_RESET_HIGH_CPU_FREQ_OFFS) & 0x1) << 3); |
| 707 | #elif defined(MV88F67XX) |
| 708 | cpu_freq = (reg & REG_SAMPLE_RESET_CPU_FREQ_MASK) >> |
| 709 | REG_SAMPLE_RESET_CPU_FREQ_OFFS; |
| 710 | #endif |
| 711 | #endif |
| 712 | |
| 713 | return cpu_freq; |
| 714 | } |
| 715 | |
| 716 | /* |
| 717 | * Name: ddr3_get_fab_opt |
| 718 | * Desc: read S@R and return CPU frequency |
| 719 | * Args: |
| 720 | * Notes: |
| 721 | * Returns: required value |
| 722 | */ |
| 723 | u32 ddr3_get_fab_opt(void) |
| 724 | { |
| 725 | __maybe_unused u32 reg, fab_opt; |
| 726 | |
| 727 | #if defined(MV88F672X) |
| 728 | return 0; /* No fabric */ |
| 729 | #else |
| 730 | /* Read sample at reset setting */ |
| 731 | reg = reg_read(REG_SAMPLE_RESET_LOW_ADDR); |
| 732 | fab_opt = (reg & REG_SAMPLE_RESET_FAB_MASK) >> |
| 733 | REG_SAMPLE_RESET_FAB_OFFS; |
| 734 | |
| 735 | #if defined(MV88F78X60) |
| 736 | reg = reg_read(REG_SAMPLE_RESET_HIGH_ADDR); |
| 737 | fab_opt |= (((reg >> 19) & 0x1) << 4); |
| 738 | #endif |
| 739 | |
| 740 | return fab_opt; |
| 741 | #endif |
| 742 | } |
| 743 | |
| 744 | /* |
| 745 | * Name: ddr3_get_vco_freq |
| 746 | * Desc: read S@R and return VCO frequency |
| 747 | * Args: |
| 748 | * Notes: |
| 749 | * Returns: required value |
| 750 | */ |
| 751 | u32 ddr3_get_vco_freq(void) |
| 752 | { |
| 753 | u32 fab, cpu_freq, ui_vco_freq; |
| 754 | |
| 755 | fab = ddr3_get_fab_opt(); |
| 756 | cpu_freq = ddr3_get_cpu_freq(); |
| 757 | |
| 758 | if (fab == 2 || fab == 3 || fab == 7 || fab == 8 || fab == 10 || |
| 759 | fab == 15 || fab == 17 || fab == 20) |
| 760 | ui_vco_freq = cpu_freq + CLK_CPU; |
| 761 | else |
| 762 | ui_vco_freq = cpu_freq; |
| 763 | |
| 764 | return ui_vco_freq; |
| 765 | } |
| 766 | |
| 767 | #ifdef STATIC_TRAINING |
| 768 | /* |
| 769 | * Name: ddr3_static_training_init - Init DDR3 Training with |
| 770 | * static parameters |
| 771 | * Desc: Use this routine to init the controller without the HW training |
| 772 | * procedure |
| 773 | * User must provide compatible header file with registers data. |
| 774 | * Args: None. |
| 775 | * Notes: |
| 776 | * Returns: None. |
| 777 | */ |
| 778 | void ddr3_static_training_init(void) |
| 779 | { |
| 780 | MV_DRAM_MODES *ddr_mode; |
| 781 | u32 reg; |
| 782 | int j; |
| 783 | |
| 784 | ddr_mode = ddr3_get_static_ddr_mode(); |
| 785 | |
| 786 | j = 0; |
| 787 | while (ddr_mode->vals[j].reg_addr != 0) { |
| 788 | udelay(10); /* haim want to delay each write */ |
| 789 | reg_write(ddr_mode->vals[j].reg_addr, |
| 790 | ddr_mode->vals[j].reg_value); |
| 791 | |
| 792 | if (ddr_mode->vals[j].reg_addr == |
| 793 | REG_PHY_REGISTRY_FILE_ACCESS_ADDR) |
| 794 | do { |
| 795 | reg = reg_read(REG_PHY_REGISTRY_FILE_ACCESS_ADDR) & |
| 796 | REG_PHY_REGISTRY_FILE_ACCESS_OP_DONE; |
| 797 | } while (reg); |
| 798 | j++; |
| 799 | } |
| 800 | } |
| 801 | #endif |
| 802 | |
| 803 | /* |
| 804 | * Name: ddr3_get_static_mc_value - Init Memory controller with static |
| 805 | * parameters |
| 806 | * Desc: Use this routine to init the controller without the HW training |
| 807 | * procedure |
| 808 | * User must provide compatible header file with registers data. |
| 809 | * Args: None. |
| 810 | * Notes: |
| 811 | * Returns: None. |
| 812 | */ |
| 813 | u32 ddr3_get_static_mc_value(u32 reg_addr, u32 offset1, u32 mask1, u32 offset2, |
| 814 | u32 mask2) |
| 815 | { |
| 816 | u32 reg, tmp; |
| 817 | |
| 818 | reg = reg_read(reg_addr); |
| 819 | |
| 820 | tmp = (reg >> offset1) & mask1; |
| 821 | if (mask2) |
| 822 | tmp |= (reg >> offset2) & mask2; |
| 823 | |
| 824 | return tmp; |
| 825 | } |
| 826 | |
| 827 | /* |
| 828 | * Name: ddr3_get_static_ddr_mode - Init Memory controller with static |
| 829 | * parameters |
| 830 | * Desc: Use this routine to init the controller without the HW training |
| 831 | * procedure |
| 832 | * User must provide compatible header file with registers data. |
| 833 | * Args: None. |
| 834 | * Notes: |
| 835 | * Returns: None. |
| 836 | */ |
| 837 | __weak MV_DRAM_MODES *ddr3_get_static_ddr_mode(void) |
| 838 | { |
| 839 | u32 chip_board_rev, i; |
| 840 | u32 size; |
| 841 | |
| 842 | /* Do not modify this code. relevant only for marvell Boards */ |
| 843 | #if defined(DB_78X60_PCAC) |
| 844 | chip_board_rev = Z1_PCAC; |
| 845 | #elif defined(DB_78X60_AMC) |
| 846 | chip_board_rev = A0_AMC; |
| 847 | #elif defined(DB_88F6710_PCAC) |
| 848 | chip_board_rev = A0_PCAC; |
| 849 | #elif defined(RD_88F6710) |
| 850 | chip_board_rev = A0_RD; |
| 851 | #elif defined(MV88F672X) |
| 852 | chip_board_rev = mv_board_id_get(); |
| 853 | #else |
| 854 | chip_board_rev = A0; |
| 855 | #endif |
| 856 | |
| 857 | size = sizeof(ddr_modes) / sizeof(MV_DRAM_MODES); |
| 858 | for (i = 0; i < size; i++) { |
| 859 | if ((ddr3_get_cpu_freq() == ddr_modes[i].cpu_freq) && |
| 860 | (ddr3_get_fab_opt() == ddr_modes[i].fab_freq) && |
| 861 | (chip_board_rev == ddr_modes[i].chip_board_rev)) |
| 862 | return &ddr_modes[i]; |
| 863 | } |
| 864 | |
| 865 | return &ddr_modes[0]; |
| 866 | } |
| 867 | |
| 868 | #ifdef DUNIT_STATIC |
| 869 | /* |
| 870 | * Name: ddr3_static_mc_init - Init Memory controller with static parameters |
| 871 | * Desc: Use this routine to init the controller without the HW training |
| 872 | * procedure |
| 873 | * User must provide compatible header file with registers data. |
| 874 | * Args: None. |
| 875 | * Notes: |
| 876 | * Returns: None. |
| 877 | */ |
| 878 | void ddr3_static_mc_init(void) |
| 879 | { |
| 880 | MV_DRAM_MODES *ddr_mode; |
| 881 | u32 reg; |
| 882 | int j; |
| 883 | |
| 884 | ddr_mode = ddr3_get_static_ddr_mode(); |
| 885 | j = 0; |
| 886 | while (ddr_mode->regs[j].reg_addr != 0) { |
| 887 | reg_write(ddr_mode->regs[j].reg_addr, |
| 888 | ddr_mode->regs[j].reg_value); |
| 889 | if (ddr_mode->regs[j].reg_addr == |
| 890 | REG_PHY_REGISTRY_FILE_ACCESS_ADDR) |
| 891 | do { |
| 892 | reg = reg_read(REG_PHY_REGISTRY_FILE_ACCESS_ADDR) & |
| 893 | REG_PHY_REGISTRY_FILE_ACCESS_OP_DONE; |
| 894 | } while (reg); |
| 895 | j++; |
| 896 | } |
| 897 | } |
| 898 | #endif |
| 899 | |
| 900 | /* |
| 901 | * Name: ddr3_check_config - Check user configurations: ECC/MultiCS |
| 902 | * Desc: |
| 903 | * Args: twsi Address |
| 904 | * Notes: Only Available for ArmadaXP/Armada 370 DB boards |
| 905 | * Returns: None. |
| 906 | */ |
| 907 | int ddr3_check_config(u32 twsi_addr, MV_CONFIG_TYPE config_type) |
| 908 | { |
| 909 | #ifdef AUTO_DETECTION_SUPPORT |
| 910 | u8 data = 0; |
| 911 | int ret; |
| 912 | int offset; |
| 913 | |
| 914 | if ((config_type == CONFIG_ECC) || (config_type == CONFIG_BUS_WIDTH)) |
| 915 | offset = 1; |
| 916 | else |
| 917 | offset = 0; |
| 918 | |
| 919 | ret = i2c_read(twsi_addr, offset, 1, (u8 *)&data, 1); |
| 920 | if (!ret) { |
| 921 | switch (config_type) { |
| 922 | case CONFIG_ECC: |
| 923 | if (data & 0x2) |
| 924 | return 1; |
| 925 | break; |
| 926 | case CONFIG_BUS_WIDTH: |
| 927 | if (data & 0x1) |
| 928 | return 1; |
| 929 | break; |
| 930 | #ifdef DB_88F6710 |
| 931 | case CONFIG_MULTI_CS: |
| 932 | if (CFG_MULTI_CS_MODE(data)) |
| 933 | return 1; |
| 934 | break; |
| 935 | #else |
| 936 | case CONFIG_MULTI_CS: |
| 937 | break; |
| 938 | #endif |
| 939 | } |
| 940 | } |
| 941 | #endif |
| 942 | |
| 943 | return 0; |
| 944 | } |
| 945 | |
| 946 | #if defined(DB_88F78X60_REV2) |
| 947 | /* |
| 948 | * Name: ddr3_get_eprom_fabric - Get Fabric configuration from EPROM |
| 949 | * Desc: |
| 950 | * Args: twsi Address |
| 951 | * Notes: Only Available for ArmadaXP DB Rev2 boards |
| 952 | * Returns: None. |
| 953 | */ |
| 954 | u8 ddr3_get_eprom_fabric(void) |
| 955 | { |
| 956 | #ifdef AUTO_DETECTION_SUPPORT |
| 957 | u8 data = 0; |
| 958 | int ret; |
| 959 | |
| 960 | ret = i2c_read(NEW_FABRIC_TWSI_ADDR, 1, 1, (u8 *)&data, 1); |
| 961 | if (!ret) |
| 962 | return data & 0x1F; |
| 963 | #endif |
| 964 | |
| 965 | return 0; |
| 966 | } |
| 967 | |
| 968 | #endif |
| 969 | |
| 970 | /* |
| 971 | * Name: ddr3_cl_to_valid_cl - this return register matching CL value |
| 972 | * Desc: |
| 973 | * Args: clValue - the value |
| 974 | |
| 975 | * Notes: |
| 976 | * Returns: required CL value |
| 977 | */ |
| 978 | u32 ddr3_cl_to_valid_cl(u32 cl) |
| 979 | { |
| 980 | switch (cl) { |
| 981 | case 5: |
| 982 | return 2; |
| 983 | break; |
| 984 | case 6: |
| 985 | return 4; |
| 986 | break; |
| 987 | case 7: |
| 988 | return 6; |
| 989 | break; |
| 990 | case 8: |
| 991 | return 8; |
| 992 | break; |
| 993 | case 9: |
| 994 | return 10; |
| 995 | break; |
| 996 | case 10: |
| 997 | return 12; |
| 998 | break; |
| 999 | case 11: |
| 1000 | return 14; |
| 1001 | break; |
| 1002 | case 12: |
| 1003 | return 1; |
| 1004 | break; |
| 1005 | case 13: |
| 1006 | return 3; |
| 1007 | break; |
| 1008 | case 14: |
| 1009 | return 5; |
| 1010 | break; |
| 1011 | default: |
| 1012 | return 2; |
| 1013 | } |
| 1014 | } |
| 1015 | |
| 1016 | /* |
| 1017 | * Name: ddr3_cl_to_valid_cl - this return register matching CL value |
| 1018 | * Desc: |
| 1019 | * Args: clValue - the value |
| 1020 | * Notes: |
| 1021 | * Returns: required CL value |
| 1022 | */ |
| 1023 | u32 ddr3_valid_cl_to_cl(u32 ui_valid_cl) |
| 1024 | { |
| 1025 | switch (ui_valid_cl) { |
| 1026 | case 1: |
| 1027 | return 12; |
| 1028 | break; |
| 1029 | case 2: |
| 1030 | return 5; |
| 1031 | break; |
| 1032 | case 3: |
| 1033 | return 13; |
| 1034 | break; |
| 1035 | case 4: |
| 1036 | return 6; |
| 1037 | break; |
| 1038 | case 5: |
| 1039 | return 14; |
| 1040 | break; |
| 1041 | case 6: |
| 1042 | return 7; |
| 1043 | break; |
| 1044 | case 8: |
| 1045 | return 8; |
| 1046 | break; |
| 1047 | case 10: |
| 1048 | return 9; |
| 1049 | break; |
| 1050 | case 12: |
| 1051 | return 10; |
| 1052 | break; |
| 1053 | case 14: |
| 1054 | return 11; |
| 1055 | break; |
| 1056 | default: |
| 1057 | return 0; |
| 1058 | } |
| 1059 | } |
| 1060 | |
| 1061 | /* |
| 1062 | * Name: ddr3_get_cs_num_from_reg |
| 1063 | * Desc: |
| 1064 | * Args: |
| 1065 | * Notes: |
| 1066 | * Returns: |
| 1067 | */ |
| 1068 | u32 ddr3_get_cs_num_from_reg(void) |
| 1069 | { |
| 1070 | u32 cs_ena = ddr3_get_cs_ena_from_reg(); |
| 1071 | u32 cs_count = 0; |
| 1072 | u32 cs; |
| 1073 | |
| 1074 | for (cs = 0; cs < MAX_CS; cs++) { |
| 1075 | if (cs_ena & (1 << cs)) |
| 1076 | cs_count++; |
| 1077 | } |
| 1078 | |
| 1079 | return cs_count; |
| 1080 | } |
| 1081 | |
| 1082 | /* |
| 1083 | * Name: ddr3_get_cs_ena_from_reg |
| 1084 | * Desc: |
| 1085 | * Args: |
| 1086 | * Notes: |
| 1087 | * Returns: |
| 1088 | */ |
| 1089 | u32 ddr3_get_cs_ena_from_reg(void) |
| 1090 | { |
| 1091 | return reg_read(REG_DDR3_RANK_CTRL_ADDR) & |
| 1092 | REG_DDR3_RANK_CTRL_CS_ENA_MASK; |
| 1093 | } |
| 1094 | |
| 1095 | /* |
| 1096 | * mv_ctrl_rev_get - Get Marvell controller device revision number |
| 1097 | * |
| 1098 | * DESCRIPTION: |
| 1099 | * This function returns 8bit describing the device revision as defined |
| 1100 | * in PCI Express Class Code and Revision ID Register. |
| 1101 | * |
| 1102 | * INPUT: |
| 1103 | * None. |
| 1104 | * |
| 1105 | * OUTPUT: |
| 1106 | * None. |
| 1107 | * |
| 1108 | * RETURN: |
| 1109 | * 8bit desscribing Marvell controller revision number |
| 1110 | * |
| 1111 | */ |
| 1112 | #if !defined(MV88F672X) |
| 1113 | u8 mv_ctrl_rev_get(void) |
| 1114 | { |
| 1115 | u8 rev_num; |
| 1116 | |
| 1117 | #if defined(MV_INCLUDE_CLK_PWR_CNTRL) |
| 1118 | /* Check pex power state */ |
| 1119 | u32 pex_power; |
| 1120 | pex_power = mv_ctrl_pwr_clck_get(PEX_UNIT_ID, 0); |
| 1121 | if (pex_power == 0) |
| 1122 | mv_ctrl_pwr_clck_set(PEX_UNIT_ID, 0, 1); |
| 1123 | #endif |
| 1124 | rev_num = (u8)reg_read(PEX_CFG_DIRECT_ACCESS(0, |
| 1125 | PCI_CLASS_CODE_AND_REVISION_ID)); |
| 1126 | |
| 1127 | #if defined(MV_INCLUDE_CLK_PWR_CNTRL) |
| 1128 | /* Return to power off state */ |
| 1129 | if (pex_power == 0) |
| 1130 | mv_ctrl_pwr_clck_set(PEX_UNIT_ID, 0, 0); |
| 1131 | #endif |
| 1132 | |
| 1133 | return (rev_num & PCCRIR_REVID_MASK) >> PCCRIR_REVID_OFFS; |
| 1134 | } |
| 1135 | |
| 1136 | #endif |
| 1137 | |
| 1138 | #if defined(MV88F672X) |
| 1139 | void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps) |
| 1140 | { |
| 1141 | u32 tmp, hclk; |
| 1142 | |
| 1143 | switch (freq_mode) { |
| 1144 | case CPU_333MHz_DDR_167MHz_L2_167MHz: |
| 1145 | hclk = 84; |
| 1146 | tmp = DDR_100; |
| 1147 | break; |
| 1148 | case CPU_266MHz_DDR_266MHz_L2_133MHz: |
| 1149 | case CPU_333MHz_DDR_222MHz_L2_167MHz: |
| 1150 | case CPU_400MHz_DDR_200MHz_L2_200MHz: |
| 1151 | case CPU_400MHz_DDR_267MHz_L2_200MHz: |
| 1152 | case CPU_533MHz_DDR_267MHz_L2_267MHz: |
| 1153 | case CPU_500MHz_DDR_250MHz_L2_250MHz: |
| 1154 | case CPU_600MHz_DDR_300MHz_L2_300MHz: |
| 1155 | case CPU_800MHz_DDR_267MHz_L2_400MHz: |
| 1156 | case CPU_900MHz_DDR_300MHz_L2_450MHz: |
| 1157 | tmp = DDR_300; |
| 1158 | hclk = 150; |
| 1159 | break; |
| 1160 | case CPU_333MHz_DDR_333MHz_L2_167MHz: |
| 1161 | case CPU_500MHz_DDR_334MHz_L2_250MHz: |
| 1162 | case CPU_666MHz_DDR_333MHz_L2_333MHz: |
| 1163 | tmp = DDR_333; |
| 1164 | hclk = 165; |
| 1165 | break; |
| 1166 | case CPU_533MHz_DDR_356MHz_L2_267MHz: |
| 1167 | tmp = DDR_360; |
| 1168 | hclk = 180; |
| 1169 | break; |
| 1170 | case CPU_400MHz_DDR_400MHz_L2_200MHz: |
| 1171 | case CPU_600MHz_DDR_400MHz_L2_300MHz: |
| 1172 | case CPU_800MHz_DDR_400MHz_L2_400MHz: |
| 1173 | case CPU_400MHz_DDR_400MHz_L2_400MHz: |
| 1174 | tmp = DDR_400; |
| 1175 | hclk = 200; |
| 1176 | break; |
| 1177 | case CPU_666MHz_DDR_444MHz_L2_333MHz: |
| 1178 | case CPU_900MHz_DDR_450MHz_L2_450MHz: |
| 1179 | tmp = DDR_444; |
| 1180 | hclk = 222; |
| 1181 | break; |
| 1182 | case CPU_500MHz_DDR_500MHz_L2_250MHz: |
| 1183 | case CPU_1000MHz_DDR_500MHz_L2_500MHz: |
| 1184 | case CPU_1000MHz_DDR_500MHz_L2_333MHz: |
| 1185 | tmp = DDR_500; |
| 1186 | hclk = 250; |
| 1187 | break; |
| 1188 | case CPU_533MHz_DDR_533MHz_L2_267MHz: |
| 1189 | case CPU_800MHz_DDR_534MHz_L2_400MHz: |
| 1190 | case CPU_1100MHz_DDR_550MHz_L2_550MHz: |
| 1191 | tmp = DDR_533; |
| 1192 | hclk = 267; |
| 1193 | break; |
| 1194 | case CPU_600MHz_DDR_600MHz_L2_300MHz: |
| 1195 | case CPU_900MHz_DDR_600MHz_L2_450MHz: |
| 1196 | case CPU_1200MHz_DDR_600MHz_L2_600MHz: |
| 1197 | tmp = DDR_600; |
| 1198 | hclk = 300; |
| 1199 | break; |
| 1200 | case CPU_666MHz_DDR_666MHz_L2_333MHz: |
| 1201 | case CPU_1000MHz_DDR_667MHz_L2_500MHz: |
| 1202 | tmp = DDR_666; |
| 1203 | hclk = 333; |
| 1204 | break; |
| 1205 | default: |
| 1206 | *ddr_freq = 0; |
| 1207 | *hclk_ps = 0; |
| 1208 | break; |
| 1209 | } |
| 1210 | |
| 1211 | *ddr_freq = tmp; /* DDR freq define */ |
| 1212 | *hclk_ps = 1000000 / hclk; /* values are 1/HCLK in ps */ |
| 1213 | |
| 1214 | return; |
| 1215 | } |
| 1216 | #endif |