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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Fabio Estevamadac83a2011-09-06 09:05:43 +00002/*
3 * (C) Copyright 2011 Freescale Semiconductor, Inc.
4 *
5 * Author: Fabio Estevam <fabio.estevam@freescale.com>
Fabio Estevamadac83a2011-09-06 09:05:43 +00006 */
7
8#include <common.h>
Simon Glassa7b51302019-11-14 12:57:46 -07009#include <init.h>
Fabio Estevamadac83a2011-09-06 09:05:43 +000010#include <asm/io.h>
Fabio Estevam1de48fa2012-10-23 06:34:49 +000011#include <asm/gpio.h>
Fabio Estevamadac83a2011-09-06 09:05:43 +000012#include <asm/arch/imx-regs.h>
Benoît Thébaudeaua12f2222013-05-03 10:32:14 +000013#include <asm/arch/iomux-mx25.h>
Fabio Estevam1de48fa2012-10-23 06:34:49 +000014#include <asm/arch/clock.h>
15#include <mmc.h>
Yangbo Lu73340382019-06-21 11:42:28 +080016#include <fsl_esdhc_imx.h>
Fabio Estevam90c3aae2012-10-23 06:34:53 +000017#include <i2c.h>
Simon Glassdbd79542020-05-10 11:40:11 -060018#include <linux/delay.h>
Fabio Estevam592fd4e2012-12-11 04:58:02 +000019#include <power/pmic.h>
Fabio Estevam90c3aae2012-10-23 06:34:53 +000020#include <fsl_pmic.h>
21#include <mc34704.h>
Fabio Estevam1de48fa2012-10-23 06:34:49 +000022
Benoît Thébaudeau518e7a92013-05-03 10:32:15 +000023#define FEC_RESET_B IMX_GPIO_NR(4, 8)
24#define FEC_ENABLE_B IMX_GPIO_NR(2, 3)
Fabio Estevam1de48fa2012-10-23 06:34:49 +000025#define CARD_DETECT IMX_GPIO_NR(2, 1)
Fabio Estevamadac83a2011-09-06 09:05:43 +000026
27DECLARE_GLOBAL_DATA_PTR;
28
Yangbo Lu73340382019-06-21 11:42:28 +080029#ifdef CONFIG_FSL_ESDHC_IMX
Fabio Estevam1de48fa2012-10-23 06:34:49 +000030struct fsl_esdhc_cfg esdhc_cfg[1] = {
31 {IMX_MMC_SDHC1_BASE},
32};
33#endif
34
Benoît Thébaudeaua12f2222013-05-03 10:32:14 +000035/*
36 * FIXME: need to revisit this
37 * The original code enabled PUE and 100-k pull-down without PKE, so the right
38 * value here is likely:
39 * 0 for no pull
40 * or:
41 * PAD_CTL_PUS_100K_DOWN for 100-k pull-down
42 */
43#define FEC_OUT_PAD_CTRL 0
44
45#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
46 PAD_CTL_ODE)
47
Fabio Estevam90c3aae2012-10-23 06:34:53 +000048static void mx25pdk_fec_init(void)
49{
Benoît Thébaudeaua12f2222013-05-03 10:32:14 +000050 static const iomux_v3_cfg_t fec_pads[] = {
51 MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
52 MX25_PAD_FEC_RX_DV__FEC_RX_DV,
53 MX25_PAD_FEC_RDATA0__FEC_RDATA0,
54 NEW_PAD_CTRL(MX25_PAD_FEC_TDATA0__FEC_TDATA0, FEC_OUT_PAD_CTRL),
55 NEW_PAD_CTRL(MX25_PAD_FEC_TX_EN__FEC_TX_EN, FEC_OUT_PAD_CTRL),
56 NEW_PAD_CTRL(MX25_PAD_FEC_MDC__FEC_MDC, FEC_OUT_PAD_CTRL),
57 MX25_PAD_FEC_MDIO__FEC_MDIO,
58 MX25_PAD_FEC_RDATA1__FEC_RDATA1,
59 NEW_PAD_CTRL(MX25_PAD_FEC_TDATA1__FEC_TDATA1, FEC_OUT_PAD_CTRL),
Fabio Estevam90c3aae2012-10-23 06:34:53 +000060
Benoît Thébaudeaua12f2222013-05-03 10:32:14 +000061 NEW_PAD_CTRL(MX25_PAD_D12__GPIO_4_8, 0), /* FEC_RESET_B */
62 NEW_PAD_CTRL(MX25_PAD_A17__GPIO_2_3, 0), /* FEC_ENABLE_B */
63 };
Fabio Estevam90c3aae2012-10-23 06:34:53 +000064
Benoît Thébaudeaua12f2222013-05-03 10:32:14 +000065 static const iomux_v3_cfg_t i2c_pads[] = {
66 NEW_PAD_CTRL(MX25_PAD_I2C1_CLK__I2C1_CLK, I2C_PAD_CTRL),
67 NEW_PAD_CTRL(MX25_PAD_I2C1_DAT__I2C1_DAT, I2C_PAD_CTRL),
68 };
Fabio Estevam90c3aae2012-10-23 06:34:53 +000069
Benoît Thébaudeaua12f2222013-05-03 10:32:14 +000070 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
Fabio Estevam90c3aae2012-10-23 06:34:53 +000071
72 /* Assert RESET and ENABLE low */
73 gpio_direction_output(FEC_RESET_B, 0);
74 gpio_direction_output(FEC_ENABLE_B, 0);
75
76 udelay(10);
77
78 /* Deassert RESET and ENABLE */
79 gpio_set_value(FEC_RESET_B, 1);
80 gpio_set_value(FEC_ENABLE_B, 1);
81
82 /* Setup I2C pins so that PMIC can turn on PHY supply */
Benoît Thébaudeaua12f2222013-05-03 10:32:14 +000083 imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
Fabio Estevam90c3aae2012-10-23 06:34:53 +000084}
85
Fabio Estevamadac83a2011-09-06 09:05:43 +000086int dram_init(void)
87{
88 /* dram_init must store complete ramsize in gd->ram_size */
89 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
90 PHYS_SDRAM_1_SIZE);
91 return 0;
92}
93
Benoît Thébaudeaua12f2222013-05-03 10:32:14 +000094/*
95 * Set up input pins with hysteresis and 100-k pull-ups
96 */
97#define UART1_IN_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP)
98/*
99 * FIXME: need to revisit this
100 * The original code enabled PUE and 100-k pull-down without PKE, so the right
101 * value here is likely:
102 * 0 for no pull
103 * or:
104 * PAD_CTL_PUS_100K_DOWN for 100-k pull-down
105 */
106#define UART1_OUT_PAD_CTRL 0
107
108static void mx25pdk_uart1_init(void)
109{
110 static const iomux_v3_cfg_t uart1_pads[] = {
111 NEW_PAD_CTRL(MX25_PAD_UART1_RXD__UART1_RXD, UART1_IN_PAD_CTRL),
112 NEW_PAD_CTRL(MX25_PAD_UART1_TXD__UART1_TXD, UART1_OUT_PAD_CTRL),
113 NEW_PAD_CTRL(MX25_PAD_UART1_RTS__UART1_RTS, UART1_OUT_PAD_CTRL),
114 NEW_PAD_CTRL(MX25_PAD_UART1_CTS__UART1_CTS, UART1_IN_PAD_CTRL),
115 };
116
117 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
118}
119
Fabio Estevamadac83a2011-09-06 09:05:43 +0000120int board_early_init_f(void)
121{
Benoît Thébaudeaua12f2222013-05-03 10:32:14 +0000122 mx25pdk_uart1_init();
Fabio Estevamadac83a2011-09-06 09:05:43 +0000123
124 return 0;
125}
126
127int board_init(void)
128{
Fabio Estevamadac83a2011-09-06 09:05:43 +0000129 /* address of boot parameters */
130 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
131
132 return 0;
133}
Fabio Estevam1de48fa2012-10-23 06:34:49 +0000134
Fabio Estevam90c3aae2012-10-23 06:34:53 +0000135int board_late_init(void)
136{
137 struct pmic *p;
Fabio Estevam592fd4e2012-12-11 04:58:02 +0000138 int ret;
Fabio Estevam90c3aae2012-10-23 06:34:53 +0000139
140 mx25pdk_fec_init();
141
Fabio Estevamf330cec2013-11-20 21:17:36 -0200142 ret = pmic_init(I2C_0);
Fabio Estevam592fd4e2012-12-11 04:58:02 +0000143 if (ret)
144 return ret;
145
146 p = pmic_get("FSL_PMIC");
147 if (!p)
148 return -ENODEV;
149
Fabio Estevam4eb32c22015-02-21 17:22:50 -0200150 /* Turn on Ethernet PHY and LCD supplies */
151 pmic_reg_write(p, MC34704_GENERAL2_REG, ONOFFE | ONOFFA);
Fabio Estevam90c3aae2012-10-23 06:34:53 +0000152
153 return 0;
154}
155
Yangbo Lu73340382019-06-21 11:42:28 +0800156#ifdef CONFIG_FSL_ESDHC_IMX
Fabio Estevam1de48fa2012-10-23 06:34:49 +0000157int board_mmc_getcd(struct mmc *mmc)
158{
Benoît Thébaudeaua12f2222013-05-03 10:32:14 +0000159 /* Set up the Card Detect pin. */
160 imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX25_PAD_A15__GPIO_2_1, 0));
Fabio Estevam1de48fa2012-10-23 06:34:49 +0000161
162 gpio_direction_input(CARD_DETECT);
163 return !gpio_get_value(CARD_DETECT);
164}
165
166int board_mmc_init(bd_t *bis)
167{
Benoît Thébaudeaua12f2222013-05-03 10:32:14 +0000168 static const iomux_v3_cfg_t sdhc1_pads[] = {
169 NEW_PAD_CTRL(MX25_PAD_SD1_CMD__SD1_CMD, NO_PAD_CTRL),
170 NEW_PAD_CTRL(MX25_PAD_SD1_CLK__SD1_CLK, NO_PAD_CTRL),
171 NEW_PAD_CTRL(MX25_PAD_SD1_DATA0__SD1_DATA0, NO_PAD_CTRL),
172 NEW_PAD_CTRL(MX25_PAD_SD1_DATA1__SD1_DATA1, NO_PAD_CTRL),
173 NEW_PAD_CTRL(MX25_PAD_SD1_DATA2__SD1_DATA2, NO_PAD_CTRL),
174 NEW_PAD_CTRL(MX25_PAD_SD1_DATA3__SD1_DATA3, NO_PAD_CTRL),
175 };
Fabio Estevam1de48fa2012-10-23 06:34:49 +0000176
Benoît Thébaudeaua12f2222013-05-03 10:32:14 +0000177 imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
Fabio Estevam1de48fa2012-10-23 06:34:49 +0000178
Benoît Thébaudeau2e0071b2017-05-03 11:59:06 +0200179 /*
180 * Set the eSDHC1 PER clock to the maximum frequency lower than or equal
181 * to 50 MHz that can be obtained, which requires to use UPLL as the
182 * clock source. This actually gives 48 MHz.
183 */
184 imx_set_perclk(MXC_ESDHC1_CLK, true, 50000000);
Fabio Estevam1de48fa2012-10-23 06:34:49 +0000185 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
186 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
187}
188#endif
Fabio Estevamadac83a2011-09-06 09:05:43 +0000189
190int checkboard(void)
191{
192 puts("Board: MX25PDK\n");
193
194 return 0;
195}
Fabio Estevam1385f462016-01-11 18:09:15 -0200196
197/* Lowlevel init isn't used on mx25pdk, so just provide a dummy one here */
198void lowlevel_init(void) {}