blob: d160ce4c999e0ed2ec9bc573c554824e4d61868c [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Tom Warrenf80dd822015-02-02 13:22:29 -07002/*
3 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
Tom Warrenf80dd822015-02-02 13:22:29 -07004 */
5
6#define pr_fmt(fmt) "tegra-xusb-padctl: " fmt
7
8#include <common.h>
9#include <errno.h>
Simon Glass0f2af882020-05-10 11:40:05 -060010#include <log.h>
Simon Glasscf0c6e22017-07-25 08:29:59 -060011#include <dm/of_access.h>
12#include <dm/ofnode.h>
Simon Glassdbd79542020-05-10 11:40:11 -060013#include <linux/delay.h>
Tom Warrenf80dd822015-02-02 13:22:29 -070014
Stephen Warren7de245d2015-10-23 10:50:51 -060015#include "../xusb-padctl-common.h"
Tom Warrenf80dd822015-02-02 13:22:29 -070016
17#include <asm/arch/clock.h>
Tom Warrenf80dd822015-02-02 13:22:29 -070018
19#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
20
Simon Glasscf0c6e22017-07-25 08:29:59 -060021DECLARE_GLOBAL_DATA_PTR;
22
Stephen Warrene3ba5692015-10-23 10:50:52 -060023enum tegra210_function {
24 TEGRA210_FUNC_SNPS,
25 TEGRA210_FUNC_XUSB,
26 TEGRA210_FUNC_UART,
27 TEGRA210_FUNC_PCIE_X1,
28 TEGRA210_FUNC_PCIE_X4,
29 TEGRA210_FUNC_USB3,
30 TEGRA210_FUNC_SATA,
31 TEGRA210_FUNC_RSVD,
32};
33
34static const char *const tegra210_functions[] = {
35 "snps",
36 "xusb",
37 "uart",
38 "pcie-x1",
39 "pcie-x4",
40 "usb3",
41 "sata",
42 "rsvd",
43};
44
45static const unsigned int tegra210_otg_functions[] = {
46 TEGRA210_FUNC_SNPS,
47 TEGRA210_FUNC_XUSB,
48 TEGRA210_FUNC_UART,
49 TEGRA210_FUNC_RSVD,
50};
51
52static const unsigned int tegra210_usb_functions[] = {
53 TEGRA210_FUNC_SNPS,
54 TEGRA210_FUNC_XUSB,
55};
56
57static const unsigned int tegra210_pci_functions[] = {
58 TEGRA210_FUNC_PCIE_X1,
59 TEGRA210_FUNC_USB3,
60 TEGRA210_FUNC_SATA,
61 TEGRA210_FUNC_PCIE_X4,
62};
63
64#define TEGRA210_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \
65 { \
66 .name = _name, \
67 .offset = _offset, \
68 .shift = _shift, \
69 .mask = _mask, \
70 .iddq = _iddq, \
71 .num_funcs = ARRAY_SIZE(tegra210_##_funcs##_functions), \
72 .funcs = tegra210_##_funcs##_functions, \
73 }
74
75static const struct tegra_xusb_padctl_lane tegra210_lanes[] = {
76 TEGRA210_LANE("otg-0", 0x004, 0, 0x3, 0, otg),
77 TEGRA210_LANE("otg-1", 0x004, 2, 0x3, 0, otg),
78 TEGRA210_LANE("otg-2", 0x004, 4, 0x3, 0, otg),
79 TEGRA210_LANE("otg-3", 0x004, 6, 0x3, 0, otg),
80 TEGRA210_LANE("usb2-bias", 0x004, 18, 0x3, 0, otg),
81 TEGRA210_LANE("hsic-0", 0x004, 14, 0x1, 0, usb),
82 TEGRA210_LANE("hsic-1", 0x004, 15, 0x1, 0, usb),
83 TEGRA210_LANE("pcie-0", 0x028, 12, 0x3, 1, pci),
84 TEGRA210_LANE("pcie-1", 0x028, 14, 0x3, 2, pci),
85 TEGRA210_LANE("pcie-2", 0x028, 16, 0x3, 3, pci),
86 TEGRA210_LANE("pcie-3", 0x028, 18, 0x3, 4, pci),
87 TEGRA210_LANE("pcie-4", 0x028, 20, 0x3, 5, pci),
88 TEGRA210_LANE("pcie-5", 0x028, 22, 0x3, 6, pci),
89 TEGRA210_LANE("pcie-6", 0x028, 24, 0x3, 7, pci),
90 TEGRA210_LANE("sata-0", 0x028, 30, 0x3, 8, pci),
91};
92
Tom Warrenf80dd822015-02-02 13:22:29 -070093#define XUSB_PADCTL_ELPG_PROGRAM 0x024
94#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 31)
95#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 30)
96#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 29)
97
98static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
99{
100 u32 value;
101
102 if (padctl->enable++ > 0)
103 return 0;
104
105 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
106 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
107 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
108
109 udelay(100);
110
111 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
112 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
113 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
114
115 udelay(100);
116
117 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
118 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
119 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
120
121 return 0;
122}
123
124static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
125{
126 u32 value;
127
128 if (padctl->enable == 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900129 pr_err("unbalanced enable/disable");
Tom Warrenf80dd822015-02-02 13:22:29 -0700130 return 0;
131 }
132
133 if (--padctl->enable > 0)
134 return 0;
135
136 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
137 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
138 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
139
140 udelay(100);
141
142 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
143 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
144 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
145
146 udelay(100);
147
148 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
149 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
150 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
151
152 return 0;
153}
154
155static int phy_prepare(struct tegra_xusb_phy *phy)
156{
157 int err;
158
159 err = tegra_xusb_padctl_enable(phy->padctl);
160 if (err < 0)
161 return err;
162
163 reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 0);
164
165 return 0;
166}
167
168static int phy_unprepare(struct tegra_xusb_phy *phy)
169{
170 reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 1);
171
172 return tegra_xusb_padctl_disable(phy->padctl);
173}
174
JC Kuof479aca2020-03-26 16:10:09 -0700175#define XUSB_PADCTL_USB3_PAD_MUX 0x28
176#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE (1 << 0)
177#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK0 (1 << 1)
178#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK1 (1 << 2)
179#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK2 (1 << 3)
180#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK3 (1 << 4)
181#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK4 (1 << 5)
182#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK5 (1 << 6)
183#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK6 (1 << 7)
184#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0 (1 << 8)
185
Tom Warrenf80dd822015-02-02 13:22:29 -0700186#define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360
187#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK (0xff << 20)
188#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(x) (((x) & 0xff) << 20)
189#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_MDIV_MASK (0x3 << 16)
190#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS (1 << 15)
191#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD (1 << 4)
192#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE (1 << 3)
193#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK (0x3 << 1)
194#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP(x) (((x) & 0x3) << 1)
195#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ (1 << 0)
196
197#define XUSB_PADCTL_UPHY_PLL_P0_CTL2 0x364
198#define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL_MASK (0xffffff << 4)
199#define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL(x) (((x) & 0xffffff) << 4)
200#define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD (1 << 2)
201#define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE (1 << 1)
202#define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN (1 << 0)
203
204#define XUSB_PADCTL_UPHY_PLL_P0_CTL4 0x36c
205#define XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_EN (1 << 15)
206#define XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL_MASK (0x3 << 12)
207#define XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL(x) (((x) & 0x3) << 12)
208#define XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLKBUF_EN (1 << 8)
209#define XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLK_SEL_MASK (0xf << 4)
210
211#define XUSB_PADCTL_UPHY_PLL_P0_CTL5 0x370
212#define XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL_MASK (0xff << 16)
213#define XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL(x) (((x) & 0xff) << 16)
214
215#define XUSB_PADCTL_UPHY_PLL_P0_CTL8 0x37c
216#define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE (1 << 31)
217#define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD (1 << 15)
218#define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN (1 << 13)
219#define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN (1 << 12)
220
221#define CLK_RST_XUSBIO_PLL_CFG0 0x51c
222#define CLK_RST_XUSBIO_PLL_CFG0_SEQ_ENABLE (1 << 24)
223#define CLK_RST_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ (1 << 13)
224#define CLK_RST_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET (1 << 6)
225#define CLK_RST_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL (1 << 2)
226#define CLK_RST_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL (1 << 0)
227
228static int pcie_phy_enable(struct tegra_xusb_phy *phy)
229{
230 struct tegra_xusb_padctl *padctl = phy->padctl;
231 unsigned long start;
232 u32 value;
233
234 debug("> %s(phy=%p)\n", __func__, phy);
235
236 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
237 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL_MASK;
238 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL(0x136);
239 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
240
241 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
242 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL_MASK;
243 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL(0x2a);
244 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
245
246 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
247 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD;
248 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
249
250 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
251 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD;
252 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
253
254 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
255 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD;
256 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
257
258 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
259 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL_MASK;
260 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLK_SEL_MASK;
261 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL(2);
262 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_EN;
263 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
264
265 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
266 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_MDIV_MASK;
267 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK;
268 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(25);
269 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
270
271 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
272 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ;
273 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
274
275 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
276 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK;
277 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
278
279 udelay(1);
280
281 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
282 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLKBUF_EN;
283 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
284
285 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
286 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN;
287 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
288
289 debug(" waiting for calibration\n");
290
291 start = get_timer(0);
292
293 while (get_timer(start) < 250) {
294 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
295 if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE)
296 break;
297 }
Stephen Warren6f6ed1b2015-10-23 10:50:53 -0600298 if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE)) {
299 debug(" timeout\n");
300 return -ETIMEDOUT;
301 }
Tom Warrenf80dd822015-02-02 13:22:29 -0700302 debug(" done\n");
303
304 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
305 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN;
306 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
307
308 debug(" waiting for calibration to stop\n");
309
310 start = get_timer(0);
311
312 while (get_timer(start) < 250) {
313 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
314 if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) == 0)
315 break;
316 }
Stephen Warren6f6ed1b2015-10-23 10:50:53 -0600317 if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) {
318 debug(" timeout\n");
319 return -ETIMEDOUT;
320 }
Tom Warrenf80dd822015-02-02 13:22:29 -0700321 debug(" done\n");
322
323 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
324 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE;
325 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
326
327 debug(" waiting for PLL to lock...\n");
328 start = get_timer(0);
329
330 while (get_timer(start) < 250) {
331 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
332 if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS)
333 break;
334 }
Stephen Warren6f6ed1b2015-10-23 10:50:53 -0600335 if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS)) {
336 debug(" timeout\n");
337 return -ETIMEDOUT;
338 }
Tom Warrenf80dd822015-02-02 13:22:29 -0700339 debug(" done\n");
340
341 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
342 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN;
343 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN;
344 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
345
346 debug(" waiting for register calibration...\n");
347 start = get_timer(0);
348
349 while (get_timer(start) < 250) {
350 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
351 if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE)
352 break;
353 }
Stephen Warren6f6ed1b2015-10-23 10:50:53 -0600354 if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE)) {
355 debug(" timeout\n");
356 return -ETIMEDOUT;
357 }
Tom Warrenf80dd822015-02-02 13:22:29 -0700358 debug(" done\n");
359
360 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
361 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN;
362 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
363
364 debug(" waiting for register calibration to stop...\n");
365 start = get_timer(0);
366
367 while (get_timer(start) < 250) {
368 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
369 if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) == 0)
370 break;
371 }
Stephen Warren6f6ed1b2015-10-23 10:50:53 -0600372 if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) {
373 debug(" timeout\n");
374 return -ETIMEDOUT;
375 }
Tom Warrenf80dd822015-02-02 13:22:29 -0700376 debug(" done\n");
377
378 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
379 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN;
380 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
381
Tom Warrenf80dd822015-02-02 13:22:29 -0700382 debug("< %s()\n", __func__);
383 return 0;
384}
385
386static int pcie_phy_disable(struct tegra_xusb_phy *phy)
387{
388 return 0;
389}
390
391static const struct tegra_xusb_phy_ops pcie_phy_ops = {
392 .prepare = phy_prepare,
393 .enable = pcie_phy_enable,
394 .disable = pcie_phy_disable,
395 .unprepare = phy_unprepare,
396};
397
Stephen Warren7de245d2015-10-23 10:50:51 -0600398static struct tegra_xusb_phy tegra210_phys[] = {
399 {
400 .type = TEGRA_XUSB_PADCTL_PCIE,
401 .ops = &pcie_phy_ops,
402 .padctl = &padctl,
Tom Warrenf80dd822015-02-02 13:22:29 -0700403 },
404};
405
Stephen Warren7de245d2015-10-23 10:50:51 -0600406static const struct tegra_xusb_padctl_soc tegra210_socdata = {
Stephen Warrene3ba5692015-10-23 10:50:52 -0600407 .lanes = tegra210_lanes,
408 .num_lanes = ARRAY_SIZE(tegra210_lanes),
409 .functions = tegra210_functions,
410 .num_functions = ARRAY_SIZE(tegra210_functions),
Stephen Warren7de245d2015-10-23 10:50:51 -0600411 .phys = tegra210_phys,
412 .num_phys = ARRAY_SIZE(tegra210_phys),
413};
Tom Warrenf80dd822015-02-02 13:22:29 -0700414
Simon Glasscf0c6e22017-07-25 08:29:59 -0600415void tegra_xusb_padctl_init(void)
Tom Warrenf80dd822015-02-02 13:22:29 -0700416{
Simon Glasscf0c6e22017-07-25 08:29:59 -0600417 ofnode nodes[1];
418 int count = 0;
419 int ret;
Tom Warrenf80dd822015-02-02 13:22:29 -0700420
Simon Glasscf0c6e22017-07-25 08:29:59 -0600421 debug("%s: start\n", __func__);
422 if (of_live_active()) {
423 struct device_node *np = of_find_compatible_node(NULL, NULL,
424 "nvidia,tegra210-xusb-padctl");
Tom Warrenf80dd822015-02-02 13:22:29 -0700425
Simon Glasscf0c6e22017-07-25 08:29:59 -0600426 debug("np=%p\n", np);
427 if (np) {
428 nodes[0] = np_to_ofnode(np);
429 count = 1;
430 }
431 } else {
432 int node_offsets[1];
433 int i;
Tom Warrenf80dd822015-02-02 13:22:29 -0700434
Simon Glasscf0c6e22017-07-25 08:29:59 -0600435 count = fdtdec_find_aliases_for_id(gd->fdt_blob, "padctl",
436 COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL,
437 node_offsets, ARRAY_SIZE(node_offsets));
438 for (i = 0; i < count; i++)
439 nodes[i] = offset_to_ofnode(node_offsets[i]);
440 }
441
442 ret = tegra_xusb_process_nodes(nodes, count, &tegra210_socdata);
443 debug("%s: done, ret=%d\n", __func__, ret);
Tom Warrenf80dd822015-02-02 13:22:29 -0700444}
JC Kuof479aca2020-03-26 16:10:09 -0700445
446void tegra_xusb_padctl_exit(void)
447{
448 u32 value;
449
450 debug("> %s\n", __func__);
451
452 value = padctl_readl(&padctl, XUSB_PADCTL_USB3_PAD_MUX);
453 value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE;
454 value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK0;
455 value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK1;
456 value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK2;
457 value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK3;
458 value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK4;
459 value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK5;
460 value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK6;
461 value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0;
462 padctl_writel(&padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
463
464 value = padctl_readl(&padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
465 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ;
466 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK;
467 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP(3);
468 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE;
469 padctl_writel(&padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
470
471 reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 1);
472 while (padctl.enable)
473 tegra_xusb_padctl_disable(&padctl);
474
475 debug("< %s()\n", __func__);
476}