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git01.mediatek.com / filogic / uboot / dba3e131bcfeb3495d5e6fdbe6f5cd97fa0dc617 / . / board / Marvell / sheevaplug / sheevaplug.c
blob: 23e761d5febf28c1dfb2d77a12794fa0c6762956 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]2/*
Tony Dinh3bbf1272022-04-17 16:42:32 -0700[diff] [blame]3 * Copyright (C) 2021-2022 Tony Dinh <mibodhi@gmail.com>
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]4 * (C) Copyright 2009
5 * Marvell Semiconductor <www.marvell.com>
6 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]7 */
8
Simon Glass97589732020-05-10 11:40:02 -0600[diff] [blame]9#include <init.h>
Tony Dinh3bbf1272022-04-17 16:42:32 -0700[diff] [blame]10#include <netdev.h>
Simon Glass3ba929a2020-10-30 21:38:53 -0600[diff] [blame]11#include <asm/global_data.h>
Simon Glass0ffb9d62017-05-31 19:47:48 -0600[diff] [blame]12#include <asm/mach-types.h>
Lei Wen298ae912011-10-18 20:11:42 +0530[diff] [blame]13#include <asm/arch/cpu.h>
Stefan Roesec2437842014-10-22 12:13:06 +0200[diff] [blame]14#include <asm/arch/soc.h>
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]15#include <asm/arch/mpp.h>
Tony Dinh3bbf1272022-04-17 16:42:32 -0700[diff] [blame]16#include <linux/bitops.h>
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]17
18DECLARE_GLOBAL_DATA_PTR;
19
Tony Dinh3bbf1272022-04-17 16:42:32 -0700[diff] [blame]20#define SHEEVAPLUG_OE_LOW (~(0))
21#define SHEEVAPLUG_OE_HIGH (~(0))
22#define SHEEVAPLUG_OE_VAL_LOW BIT(29) /* USB_PWEN low */
23#define SHEEVAPLUG_OE_VAL_HIGH BIT(17) /* LED pin high */
24
Prafulla Wadaskar44f4d432010-10-20 20:12:27 +0530[diff] [blame]25int board_early_init_f(void)
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]26{
27 /*
28 * default gpio configuration
29 * There are maximum 64 gpios controlled through 2 sets of registers
30 * the below configuration configures mainly initial LED status
31 */
Stefan Roesec50ab392014-10-22 12:13:11 +0200[diff] [blame]32 mvebu_config_gpio(SHEEVAPLUG_OE_VAL_LOW,
33 SHEEVAPLUG_OE_VAL_HIGH,
34 SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH);
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]35
36 /* Multi-Purpose Pins Functionality configuration */
Albert ARIBAUD4d424312012-11-26 11:27:36 +0000[diff] [blame]37 static const u32 kwmpp_config[] = {
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]38 MPP0_NF_IO2,
39 MPP1_NF_IO3,
40 MPP2_NF_IO4,
41 MPP3_NF_IO5,
42 MPP4_NF_IO6,
43 MPP5_NF_IO7,
44 MPP6_SYSRST_OUTn,
45 MPP7_GPO,
46 MPP8_UART0_RTS,
47 MPP9_UART0_CTS,
48 MPP10_UART0_TXD,
49 MPP11_UART0_RXD,
50 MPP12_SD_CLK,
51 MPP13_SD_CMD,
52 MPP14_SD_D0,
53 MPP15_SD_D1,
54 MPP16_SD_D2,
55 MPP17_SD_D3,
56 MPP18_NF_IO0,
57 MPP19_NF_IO1,
58 MPP20_GPIO,
59 MPP21_GPIO,
60 MPP22_GPIO,
61 MPP23_GPIO,
62 MPP24_GPIO,
63 MPP25_GPIO,
64 MPP26_GPIO,
65 MPP27_GPIO,
66 MPP28_GPIO,
67 MPP29_TSMP9,
68 MPP30_GPIO,
69 MPP31_GPIO,
70 MPP32_GPIO,
71 MPP33_GPIO,
72 MPP34_GPIO,
73 MPP35_GPIO,
74 MPP36_GPIO,
75 MPP37_GPIO,
76 MPP38_GPIO,
77 MPP39_GPIO,
78 MPP40_GPIO,
79 MPP41_GPIO,
80 MPP42_GPIO,
81 MPP43_GPIO,
82 MPP44_GPIO,
83 MPP45_GPIO,
84 MPP46_GPIO,
85 MPP47_GPIO,
86 MPP48_GPIO,
87 MPP49_GPIO,
88 0
89 };
Valentin Longchamp7d0d5022012-06-01 01:31:00 +0000[diff] [blame]90 kirkwood_mpp_conf(kwmpp_config, NULL);
Prafulla Wadaskar44f4d432010-10-20 20:12:27 +0530[diff] [blame]91 return 0;
92}
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]93
Tony Dinh3bbf1272022-04-17 16:42:32 -0700[diff] [blame]94int board_eth_init(struct bd_info *bis)
95{
96 return cpu_eth_init(bis);
97}
98
Prafulla Wadaskar44f4d432010-10-20 20:12:27 +0530[diff] [blame]99int board_init(void)
100{
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]101 /*
102 * arch number of board
103 */
104 gd->bd->bi_arch_number = MACH_TYPE_SHEEVAPLUG;
105
Tony Dinh3bbf1272022-04-17 16:42:32 -0700[diff] [blame]106 /* address of boot parameters */
Stefan Roese0b741752014-10-22 12:13:13 +0200[diff] [blame]107 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]108
109 return 0;
110}