Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Patrice Chotard | 5c121e1 | 2017-09-13 18:00:07 +0200 | [diff] [blame] | 2 | /* |
Patrice Chotard | 789ee0e | 2017-10-23 09:53:58 +0200 | [diff] [blame] | 3 | * Copyright (C) 2017, STMicroelectronics - All Rights Reserved |
Patrice Chotard | 5d9950d | 2020-12-02 18:47:30 +0100 | [diff] [blame] | 4 | * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. |
Patrice Chotard | 5c121e1 | 2017-09-13 18:00:07 +0200 | [diff] [blame] | 5 | */ |
| 6 | |
Patrick Delaunay | ecb23b5 | 2020-11-06 19:01:48 +0100 | [diff] [blame] | 7 | #define LOG_CATEGORY UCLASS_RESET |
| 8 | |
Patrice Chotard | 5c121e1 | 2017-09-13 18:00:07 +0200 | [diff] [blame] | 9 | #include <common.h> |
| 10 | #include <dm.h> |
| 11 | #include <errno.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 12 | #include <log.h> |
Simon Glass | 9bc1564 | 2020-02-03 07:36:16 -0700 | [diff] [blame] | 13 | #include <malloc.h> |
Patrice Chotard | 5c121e1 | 2017-09-13 18:00:07 +0200 | [diff] [blame] | 14 | #include <reset-uclass.h> |
Patrick Delaunay | b139a5b | 2018-07-09 15:17:20 +0200 | [diff] [blame] | 15 | #include <stm32_rcc.h> |
Patrice Chotard | 5c121e1 | 2017-09-13 18:00:07 +0200 | [diff] [blame] | 16 | #include <asm/io.h> |
Patrick Delaunay | ecb23b5 | 2020-11-06 19:01:48 +0100 | [diff] [blame] | 17 | #include <dm/device_compat.h> |
Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 18 | #include <linux/bitops.h> |
Patrice Chotard | 5c121e1 | 2017-09-13 18:00:07 +0200 | [diff] [blame] | 19 | |
Patrick Delaunay | 4290573 | 2020-10-15 15:01:11 +0200 | [diff] [blame] | 20 | /* offset of register without set/clear management */ |
| 21 | #define RCC_MP_GCR_OFFSET 0x10C |
| 22 | |
Patrick Delaunay | b925d62 | 2018-03-12 10:46:14 +0100 | [diff] [blame] | 23 | /* reset clear offset for STM32MP RCC */ |
| 24 | #define RCC_CL 0x4 |
| 25 | |
Patrice Chotard | 5c121e1 | 2017-09-13 18:00:07 +0200 | [diff] [blame] | 26 | struct stm32_reset_priv { |
| 27 | fdt_addr_t base; |
| 28 | }; |
| 29 | |
Patrice Chotard | 5c121e1 | 2017-09-13 18:00:07 +0200 | [diff] [blame] | 30 | static int stm32_reset_assert(struct reset_ctl *reset_ctl) |
| 31 | { |
| 32 | struct stm32_reset_priv *priv = dev_get_priv(reset_ctl->dev); |
Patrice Chotard | 4818697 | 2021-04-28 13:42:45 +0200 | [diff] [blame] | 33 | int bank = (reset_ctl->id / (sizeof(u32) * BITS_PER_BYTE)) * 4; |
| 34 | int offset = reset_ctl->id % (sizeof(u32) * BITS_PER_BYTE); |
Patrick Delaunay | ecb23b5 | 2020-11-06 19:01:48 +0100 | [diff] [blame] | 35 | |
| 36 | dev_dbg(reset_ctl->dev, "reset id = %ld bank = %d offset = %d)\n", |
| 37 | reset_ctl->id, bank, offset); |
Patrice Chotard | 5c121e1 | 2017-09-13 18:00:07 +0200 | [diff] [blame] | 38 | |
Patrick Delaunay | b139a5b | 2018-07-09 15:17:20 +0200 | [diff] [blame] | 39 | if (dev_get_driver_data(reset_ctl->dev) == STM32MP1) |
Patrick Delaunay | 4290573 | 2020-10-15 15:01:11 +0200 | [diff] [blame] | 40 | if (bank != RCC_MP_GCR_OFFSET) |
| 41 | /* reset assert is done in rcc set register */ |
| 42 | writel(BIT(offset), priv->base + bank); |
| 43 | else |
| 44 | clrbits_le32(priv->base + bank, BIT(offset)); |
Patrick Delaunay | b925d62 | 2018-03-12 10:46:14 +0100 | [diff] [blame] | 45 | else |
| 46 | setbits_le32(priv->base + bank, BIT(offset)); |
Patrice Chotard | 5c121e1 | 2017-09-13 18:00:07 +0200 | [diff] [blame] | 47 | |
| 48 | return 0; |
| 49 | } |
| 50 | |
| 51 | static int stm32_reset_deassert(struct reset_ctl *reset_ctl) |
| 52 | { |
| 53 | struct stm32_reset_priv *priv = dev_get_priv(reset_ctl->dev); |
Patrice Chotard | 4818697 | 2021-04-28 13:42:45 +0200 | [diff] [blame] | 54 | int bank = (reset_ctl->id / (sizeof(u32) * BITS_PER_BYTE)) * 4; |
| 55 | int offset = reset_ctl->id % (sizeof(u32) * BITS_PER_BYTE); |
Patrick Delaunay | ecb23b5 | 2020-11-06 19:01:48 +0100 | [diff] [blame] | 56 | |
| 57 | dev_dbg(reset_ctl->dev, "reset id = %ld bank = %d offset = %d)\n", |
| 58 | reset_ctl->id, bank, offset); |
Patrice Chotard | 5c121e1 | 2017-09-13 18:00:07 +0200 | [diff] [blame] | 59 | |
Patrick Delaunay | b139a5b | 2018-07-09 15:17:20 +0200 | [diff] [blame] | 60 | if (dev_get_driver_data(reset_ctl->dev) == STM32MP1) |
Patrick Delaunay | 4290573 | 2020-10-15 15:01:11 +0200 | [diff] [blame] | 61 | if (bank != RCC_MP_GCR_OFFSET) |
| 62 | /* reset deassert is done in rcc clr register */ |
| 63 | writel(BIT(offset), priv->base + bank + RCC_CL); |
| 64 | else |
| 65 | setbits_le32(priv->base + bank, BIT(offset)); |
Patrick Delaunay | b925d62 | 2018-03-12 10:46:14 +0100 | [diff] [blame] | 66 | else |
| 67 | clrbits_le32(priv->base + bank, BIT(offset)); |
Patrice Chotard | 5c121e1 | 2017-09-13 18:00:07 +0200 | [diff] [blame] | 68 | |
| 69 | return 0; |
| 70 | } |
| 71 | |
| 72 | static const struct reset_ops stm32_reset_ops = { |
Patrice Chotard | 5c121e1 | 2017-09-13 18:00:07 +0200 | [diff] [blame] | 73 | .rst_assert = stm32_reset_assert, |
| 74 | .rst_deassert = stm32_reset_deassert, |
| 75 | }; |
| 76 | |
| 77 | static int stm32_reset_probe(struct udevice *dev) |
| 78 | { |
| 79 | struct stm32_reset_priv *priv = dev_get_priv(dev); |
| 80 | |
Patrick Delaunay | b925d62 | 2018-03-12 10:46:14 +0100 | [diff] [blame] | 81 | priv->base = dev_read_addr(dev); |
| 82 | if (priv->base == FDT_ADDR_T_NONE) { |
| 83 | /* for MFD, get address of parent */ |
| 84 | priv->base = dev_read_addr(dev->parent); |
| 85 | if (priv->base == FDT_ADDR_T_NONE) |
| 86 | return -EINVAL; |
| 87 | } |
Patrice Chotard | 5c121e1 | 2017-09-13 18:00:07 +0200 | [diff] [blame] | 88 | |
| 89 | return 0; |
| 90 | } |
| 91 | |
| 92 | U_BOOT_DRIVER(stm32_rcc_reset) = { |
| 93 | .name = "stm32_rcc_reset", |
| 94 | .id = UCLASS_RESET, |
Patrice Chotard | 5c121e1 | 2017-09-13 18:00:07 +0200 | [diff] [blame] | 95 | .probe = stm32_reset_probe, |
Simon Glass | 8a2b47f | 2020-12-03 16:55:17 -0700 | [diff] [blame] | 96 | .priv_auto = sizeof(struct stm32_reset_priv), |
Patrice Chotard | 5c121e1 | 2017-09-13 18:00:07 +0200 | [diff] [blame] | 97 | .ops = &stm32_reset_ops, |
| 98 | }; |