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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Simon Guinota35cb4c2011-11-21 19:25:47 +05302/*
3 * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
Simon Guinota35cb4c2011-11-21 19:25:47 +05304 */
5
6#include <common.h>
7#include <i2c.h>
8#include <miiphy.h>
9
10#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
11
Simon Guinot13c5ae62012-09-06 10:51:42 +000012#define MII_MARVELL_PHY_PAGE 22
13
Simon Guinota35cb4c2011-11-21 19:25:47 +053014#define MV88E1116_LED_FCTRL_REG 10
15#define MV88E1116_CPRSP_CR3_REG 21
16#define MV88E1116_MAC_CTRL_REG 21
Simon Guinota35cb4c2011-11-21 19:25:47 +053017#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
18#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
19
Simon Guinot0473b682012-06-05 13:16:00 +000020void mv_phy_88e1116_init(const char *name, u16 phyaddr)
Simon Guinota35cb4c2011-11-21 19:25:47 +053021{
22 u16 reg;
Simon Guinota35cb4c2011-11-21 19:25:47 +053023
24 if (miiphy_set_current_dev(name))
25 return;
26
Simon Guinota35cb4c2011-11-21 19:25:47 +053027 /*
28 * Enable RGMII delay on Tx and Rx for CPU port
29 * Ref: sec 4.7.2 of chip datasheet
30 */
Simon Guinot13c5ae62012-09-06 10:51:42 +000031 miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 2);
Simon Guinot0473b682012-06-05 13:16:00 +000032 miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, &reg);
Simon Guinota35cb4c2011-11-21 19:25:47 +053033 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
Simon Guinot0473b682012-06-05 13:16:00 +000034 miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg);
Simon Guinot13c5ae62012-09-06 10:51:42 +000035 miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 0);
Simon Guinota35cb4c2011-11-21 19:25:47 +053036
Simon Guinot0473b682012-06-05 13:16:00 +000037 if (miiphy_reset(name, phyaddr) == 0)
38 printf("88E1116 Initialized on %s\n", name);
Simon Guinota35cb4c2011-11-21 19:25:47 +053039}
Simon Guinot13c5ae62012-09-06 10:51:42 +000040
41void mv_phy_88e1318_init(const char *name, u16 phyaddr)
42{
43 u16 reg;
44
45 if (miiphy_set_current_dev(name))
46 return;
47
48 /*
49 * Set control mode 4 for LED[0].
50 */
51 miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 3);
52 miiphy_read(name, phyaddr, 16, &reg);
53 reg |= 0xf;
54 miiphy_write(name, phyaddr, 16, reg);
55
56 /*
57 * Enable RGMII delay on Tx and Rx for CPU port
58 * Ref: sec 4.7.2 of chip datasheet
59 */
60 miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 2);
61 miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, &reg);
62 reg |= (MV88E1116_RGMII_TXTM_CTRL | MV88E1116_RGMII_RXTM_CTRL);
63 miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg);
64 miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 0);
65
66 if (miiphy_reset(name, phyaddr) == 0)
67 printf("88E1318 Initialized on %s\n", name);
68}
Simon Guinota35cb4c2011-11-21 19:25:47 +053069#endif /* CONFIG_CMD_NET && CONFIG_RESET_PHY_R */
70
71#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
72int lacie_read_mac_address(uchar *mac_addr)
73{
74 int ret;
75 ushort version;
76
77 /* I2C-0 for on-board EEPROM */
78 i2c_set_bus_num(0);
79
80 /* Check layout version for EEPROM data */
81 ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
82 CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
83 (uchar *) &version, 2);
84 if (ret != 0) {
85 printf("Error: failed to read I2C EEPROM @%02x\n",
86 CONFIG_SYS_I2C_EEPROM_ADDR);
87 return ret;
88 }
89 version = be16_to_cpu(version);
90 if (version < 1 || version > 3) {
91 printf("Error: unknown version %d for EEPROM data\n",
92 version);
93 return -1;
94 }
95
96 /* Read Ethernet MAC address from EEPROM */
97 ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 2,
98 CONFIG_SYS_I2C_EEPROM_ADDR_LEN, mac_addr, 6);
99 if (ret != 0)
100 printf("Error: failed to read I2C EEPROM @%02x\n",
101 CONFIG_SYS_I2C_EEPROM_ADDR);
102 return ret;
103}
104#endif /* CONFIG_CMD_I2C && CONFIG_SYS_I2C_EEPROM_ADDR */