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git01.mediatek.com / filogic / uboot / db3ffb0755d7395ebfa8c00b908e7ed7cee615f0 / . / arch / riscv / dts / openpiton-riscv64.dts
blob: e0553d520f2327d15ea9a10e059e38b63f36c768 [file] [log] [blame]
Tianrui Wei2ef594d2021-07-01 12:54:19 +0800[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/* Copyright (c) 2021 Tianrui Wei <tianrui-wei@outlook.com> */
3
4/*
5 * This dts is for a dual core instance of OpenPiton+Ariane built
6 * to run on a Digilent Genesys 2 FPGA at 66.67MHz. These files
7 * are automatically generated by the OpenPiton build system and
8 * this configuration may not be what you need if your configuration
9 * is different from the below.
10 */
11
12/dts-v1/;
13
14/ {
15 #address-cells = <2>;
16 #size-cells = <2>;
17 compatible = "openpiton,riscv64";
18
19 chosen {
20 stdout-path = "uart0:115200";
21 };
22
23 aliases {
24 console = &uart0;
25 serial0 = &uart0;
26 };
27
28 cpus {
29 #address-cells = <1>;
30 #size-cells = <0>;
31 timebase-frequency = <520835>;
32
33 CPU0: cpu@0 {
34 clocks = <&clk0>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]35 bootph-pre-ram;
Tianrui Wei2ef594d2021-07-01 12:54:19 +0800[diff] [blame]36 device_type = "cpu";
37 reg = <0>;
38 compatible = "openhwgroup,cva6", "riscv";
39 riscv,isa = "rv64imafdc";
40 mmu-type = "riscv,sv39";
41 tlb-split;
42 // HLIC - hart local interrupt controller
43 CPU0_intc: interrupt-controller {
44 #interrupt-cells = <1>;
45 interrupt-controller;
46 compatible = "riscv,cpu-intc";
47 };
48 };
49
50 CPU1: cpu@1 {
51 clocks = <&clk0>;
52 device_type = "cpu";
53 reg = <1>;
54 compatible = "openhwgroup,cva6", "riscv";
55 riscv,isa = "rv64imafdc";
56 mmu-type = "riscv,sv39";
57 tlb-split;
58 // HLIC - hart local interrupt controller
59 CPU1_intc: interrupt-controller {
60 #interrupt-cells = <1>;
61 interrupt-controller;
62 compatible = "riscv,cpu-intc";
63 };
64 };
65
66 };
67
68 clocks {
69 clk0: osc {
70 compatible = "fixed-clock";
71 #clock-cells = <0>;
72 clock-frequency = <66667000>;
73 };
74 };
75
76 memory@80000000 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]77 bootph-pre-ram;
Tianrui Wei2ef594d2021-07-01 12:54:19 +0800[diff] [blame]78 device_type = "memory";
79 reg = < 0x00000000 0x80000000 0x00000000 0x40000000 >;
80 };
81
82 soc {
Tianrui Weibabf1cb2021-07-07 15:48:22 +0800[diff] [blame]83 #address-cells = <2>;
84 #size-cells = <2>;
Tianrui Wei2ef594d2021-07-01 12:54:19 +0800[diff] [blame]85 compatible = "openpiton,chipset", "simple-bus";
86 ranges;
87
88 uart0: uart@fff0c2c000 {
89 compatible = "ns16550", "openpiton,ns16550";
90 reg = < 0x000000ff 0xf0c2c000 0x00000000 0x000d4000 >;
91 interrupt-parent = <&PLIC0>;
92 interrupts = <1>;
93 reg-shift = <0>;
94 // regs are spaced on 8 bit boundary
95 };
96
97 eth: ethernet@fff0d00000 {
98 compatible = "xlnx,xps-ethernetlite-1.00.a", "openpiton,ethernet";
99 device_type = "network";
100 reg = < 0x000000ff 0xf0d00000 0x00000000 0x00100000 >;
101 interrupt-parent = <&PLIC0>;
102 interrupts = <2>;
103 phy-handle = <&phy0>;
104 xlnx,duplex = <0x1>;
105 xlnx,include-global-buffers = <0x1>;
106 xlnx,include-internal-loopback = <0x0>;
107 xlnx,include-mdio = <0x1>;
108 xlnx,rx-ping-pong = <0x1>;
109 xlnx,s-axi-id-width = <0x1>;
110 xlnx,tx-ping-pong = <0x1>;
111 xlnx,use-internal = <0x0>;
112 axi_ethernetlite_0_mdio: mdio {
113 #address-cells = <1>;
114 #size-cells = <0>;
115 phy0: phy@1 {
116 compatible = "ethernet-phy-id001C.C915";
117 device_type = "ethernet-phy";
118 reg = <1>;
119 };
120 };
121 };
122
123 sdhci_0: sdhci@f000000000 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]124 bootph-pre-ram;
Tianrui Wei2ef594d2021-07-01 12:54:19 +0800[diff] [blame]125 compatible = "openpiton,piton-mmc", "openpiton,mmc";
126 reg = < 0x000000f0 0x00000000 0x00000000 0x00300000 >;
127 };
128
129 clint@fff1020000 {
130 compatible = "sifive,clint0", "openpiton,clint";
131 interrupts-extended = < &CPU0_intc 3
132 &CPU0_intc 7
133 &CPU1_intc 3
134 &CPU1_intc 7 >;
135 reg = < 0x000000ff 0xf1020000 0x00000000 0x000c0000 >;
136 clocks = <&clk0>;
137 };
138
139 PLIC0: plic@fff1100000 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]140 bootph-pre-ram;
Tianrui Wei2ef594d2021-07-01 12:54:19 +0800[diff] [blame]141 #interrupt-cells = <1>;
142 compatible = "sifive,plic-1.0.0", "openpiton,plic";
143 interrupt-controller;
144 interrupts-extended = < &CPU0_intc 11
145 &CPU0_intc 9
146 &CPU1_intc 11
147 &CPU1_intc 9 >;
148 reg = < 0x000000ff 0xf1100000 0x00000000 0x04000000 >;
149 riscv,max-priority = <7>;
150 riscv,ndev = <2>;
151 };
152 };
153};