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git01.mediatek.com / filogic / uboot / dae95a4129242f9c2d91a294377f06c2d23b4f51 / . / include / power / s2mps11.h
blob: 22b38fff7032b510d646dac4e7f00723727d8d06 [file] [log] [blame]
Przemyslaw Marczak91815122015-10-27 13:07:58 +0100[diff] [blame]1#ifndef __S2MPS11__H__
2#define __S2MPS11__H__
3
4enum s2mps11_reg {
5 S2MPS11_REG_ID = 0,
6 S2MPS11_REG_INT1,
7 S2MPS11_REG_INT2,
8 S2MPS11_REG_INT3,
9 S2MPS11_REG_INT1M,
10 S2MPS11_REG_INT2M,
11 S2MPS11_REG_INT3M,
12 S2MPS11_REG_STATUS1,
13 S2MPS11_REG_STATUS2,
14 S2MPS11_REG_OFFSRC,
15 S2MPS11_REG_PWRONSRC,
16 S2MPS11_REG_RTC_CTRL,
17 S2MPS11_REG_CTRL1,
18 S2MPS11_REG_ETC_TEST,
19 S2MPS11_REG_RSVD3,
20 S2MPS11_REG_BU_CHG,
21 S2MPS11_REG_RAMP,
22 S2MPS11_REG_RAMP_BUCK,
23 S2MPS11_REG_LDO1_8,
24 S2MPS11_REG_LDO9_16,
25 S2MPS11_REG_LDO17_24,
26 S2MPS11_REG_LDO25_32,
27 S2MPS11_REG_LDO33_38,
28 S2MPS11_REG_LDO1_8_OVC,
29 S2MPS11_REG_LDO9_16_OVC,
30 S2MPS11_REG_LDO17_24_OVC,
31 S2MPS11_REG_LDO25_32_OVC,
32 S2MPS11_REG_LDO33_38_OVC,
33 S2MPS11_REG_RESERVED1,
34 S2MPS11_REG_RESERVED2,
35 S2MPS11_REG_RESERVED3,
36 S2MPS11_REG_RESERVED4,
37 S2MPS11_REG_RESERVED5,
38 S2MPS11_REG_RESERVED6,
39 S2MPS11_REG_RESERVED7,
40 S2MPS11_REG_RESERVED8,
41 S2MPS11_REG_WDRSTEN_CTRL,
42 S2MPS11_REG_B1CTRL1,
43 S2MPS11_REG_B1CTRL2,
44 S2MPS11_REG_B2CTRL1,
45 S2MPS11_REG_B2CTRL2,
46 S2MPS11_REG_B3CTRL1,
47 S2MPS11_REG_B3CTRL2,
48 S2MPS11_REG_B4CTRL1,
49 S2MPS11_REG_B4CTRL2,
50 S2MPS11_REG_B5CTRL1,
51 S2MPS11_REG_BUCK5_SW,
52 S2MPS11_REG_B5CTRL2,
53 S2MPS11_REG_B5CTRL3,
54 S2MPS11_REG_B5CTRL4,
55 S2MPS11_REG_B5CTRL5,
56 S2MPS11_REG_B6CTRL1,
57 S2MPS11_REG_B6CTRL2,
58 S2MPS11_REG_B7CTRL1,
59 S2MPS11_REG_B7CTRL2,
60 S2MPS11_REG_B8CTRL1,
61 S2MPS11_REG_B8CTRL2,
62 S2MPS11_REG_B9CTRL1,
63 S2MPS11_REG_B9CTRL2,
64 S2MPS11_REG_B10CTRL1,
65 S2MPS11_REG_B10CTRL2,
66 S2MPS11_REG_L1CTRL,
67 S2MPS11_REG_L2CTRL,
68 S2MPS11_REG_L3CTRL,
69 S2MPS11_REG_L4CTRL,
70 S2MPS11_REG_L5CTRL,
71 S2MPS11_REG_L6CTRL,
72 S2MPS11_REG_L7CTRL,
73 S2MPS11_REG_L8CTRL,
74 S2MPS11_REG_L9CTRL,
75 S2MPS11_REG_L10CTRL,
76 S2MPS11_REG_L11CTRL,
77 S2MPS11_REG_L12CTRL,
78 S2MPS11_REG_L13CTRL,
79 S2MPS11_REG_L14CTRL,
80 S2MPS11_REG_L15CTRL,
81 S2MPS11_REG_L16CTRL,
82 S2MPS11_REG_L17CTRL,
83 S2MPS11_REG_L18CTRL,
84 S2MPS11_REG_L19CTRL,
85 S2MPS11_REG_L20CTRL,
86 S2MPS11_REG_L21CTRL,
87 S2MPS11_REG_L22CTRL,
88 S2MPS11_REG_L23CTRL,
89 S2MPS11_REG_L24CTRL,
90 S2MPS11_REG_L25CTRL,
91 S2MPS11_REG_L26CTRL,
92 S2MPS11_REG_L27CTRL,
93 S2MPS11_REG_L28CTRL,
94 S2MPS11_REG_L29CTRL,
95 S2MPS11_REG_L30CTRL,
96 S2MPS11_REG_L31CTRL,
97 S2MPS11_REG_L32CTRL,
98 S2MPS11_REG_L33CTRL,
99 S2MPS11_REG_L34CTRL,
100 S2MPS11_REG_L35CTRL,
101 S2MPS11_REG_L36CTRL,
102 S2MPS11_REG_L37CTRL,
103 S2MPS11_REG_L38CTRL,
104 S2MPS11_REG_COUNT,
105};
106
107#define S2MPS11_LDO26_ENABLE 0xec
108
Jaehoon Chung76f20082018-01-16 15:33:50 +0900[diff] [blame]109#define S2MPS11_LDO_NUM 26
110#define S2MPS11_BUCK_NUM 10
111
112/* Driver name */
113#define S2MPS11_BUCK_DRIVER "s2mps11_buck"
114#define S2MPS11_OF_BUCK_PREFIX "BUCK"
115#define S2MPS11_LDO_DRIVER "s2mps11_ldo"
116#define S2MPS11_OF_LDO_PREFIX "LDO"
117
118/* BUCK */
119#define S2MPS11_BUCK_VOLT_MASK 0xff
120#define S2MPS11_BUCK9_VOLT_MASK 0x1f
121
122#define S2MPS11_BUCK_LSTEP 6250
123#define S2MPS11_BUCK_HSTEP 12500
124#define S2MPS11_BUCK9_STEP 25000
125
126#define S2MPS11_BUCK_UV_MIN 600000
127#define S2MPS11_BUCK_UV_HMIN 750000
128#define S2MPS11_BUCK9_UV_MIN 1400000
129
130#define S2MPS11_BUCK_VOLT_MAX_HEX 0xA0
131#define S2MPS11_BUCK5_VOLT_MAX_HEX 0xDF
132#define S2MPS11_BUCK7_8_10_VOLT_MAX_HEX 0xDC
133#define S2MPS11_BUCK9_VOLT_MAX_HEX 0x5F
134
135#define S2MPS11_BUCK_MODE_SHIFT 6
136#define S2MPS11_BUCK_MODE_MASK (0x3)
137#define S2MPS11_BUCK_MODE_OFF (0x0 << 6)
138#define S2MPS11_BUCK_MODE_STANDBY (0x1 << 6)
139#define S2MPS11_BUCK_MODE_ON (0x3 << 6)
140
141/* LDO */
142#define S2MPS11_LDO_VOLT_MASK 0x3F
143#define S2MPS11_LDO_VOLT_MAX_HEX 0x3F
144
145#define S2MPS11_LDO_STEP 25000
146#define S2MPS11_LDO_UV_MIN 800000
147
148#define S2MPS11_LDO_MODE_MASK 0x3
149#define S2MPS11_LDO_MODE_SHIFT 6
150
151#define S2MPS11_LDO_MODE_OFF (0x0 << 6)
152#define S2MPS11_LDO_MODE_STANDBY (0x1 << 6)
153#define S2MPS11_LDO_MODE_STANDBY_LPM (0x2 << 6)
154#define S2MPS11_LDO_MODE_ON (0x3 << 6)
155
156enum {
157 OP_OFF = 0,
158 OP_LPM,
159 OP_STANDBY,
160 OP_STANDBY_LPM,
161 OP_ON,
162};
163
Przemyslaw Marczak91815122015-10-27 13:07:58 +0100[diff] [blame]164#endif