blob: 04951825d49d456a4f55817820066370235d022a [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Scott Wood095b7122012-09-20 19:02:18 -05002/*
3 * (C) Copyright 2006
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de
5 *
6 * Copyright 2009 Freescale Semiconductor, Inc.
Scott Wood095b7122012-09-20 19:02:18 -05007 */
8
Masahiro Yamadacd1b58e2014-04-28 10:17:10 +09009#include "config.h"
Scott Wood095b7122012-09-20 19:02:18 -050010
11OUTPUT_ARCH(powerpc)
Ying Zhang0d4f5442013-05-20 14:07:23 +080012#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
13PHDRS
14{
15 text PT_LOAD;
16 bss PT_LOAD;
17}
18#endif
Scott Wood095b7122012-09-20 19:02:18 -050019SECTIONS
20{
21 . = CONFIG_SPL_TEXT_BASE;
22 .text : {
23 *(.text*)
24 }
25 _etext = .;
26
27 .reloc : {
28 _GOT2_TABLE_ = .;
29 KEEP(*(.got2))
30 KEEP(*(.got))
Scott Wood095b7122012-09-20 19:02:18 -050031 _FIXUP_TABLE_ = .;
32 KEEP(*(.fixup))
33 }
34 __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
35 __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
36
37 . = ALIGN(8);
38 .data : {
39 *(.rodata*)
40 *(.data*)
41 *(.sdata*)
42 }
43 _edata = .;
44
Ying Zhang4393f952013-09-04 17:03:45 +080045 . = ALIGN(4);
46 .u_boot_list : {
47 KEEP(*(SORT(.u_boot_list*)));
48 }
49
Ying Zhang9ff70262013-08-16 15:16:11 +080050 . = .;
51 __start___ex_table = .;
52 __ex_table : { *(__ex_table) }
53 __stop___ex_table = .;
54
Scott Wood095b7122012-09-20 19:02:18 -050055 . = ALIGN(8);
56 __init_begin = .;
57 __init_end = .;
Prabhakar Kushwaha6e2b9a32014-04-08 19:12:31 +053058#ifdef CONFIG_SPL_SKIP_RELOCATE
59 . = ALIGN(4);
60 __bss_start = .;
61 .bss : {
62 *(.sbss*)
63 *(.bss*)
64 }
65 . = ALIGN(4);
66 __bss_end = .;
67#endif
Po Liuf6facca2014-01-10 10:10:58 +080068
69/* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */
70#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
71 .bootpg ADDR(.text) - 0x1000 :
72 {
73 KEEP(*(.bootpg))
74 } :text = 0xffff
75#else
Scott Wood095b7122012-09-20 19:02:18 -050076#if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */
Prabhakar Kushwahaa7eb72b2014-04-08 19:12:19 +053077#ifndef BOOT_PAGE_OFFSET
78#define BOOT_PAGE_OFFSET 0x1000
79#endif
80 .bootpg ADDR(.text) + BOOT_PAGE_OFFSET :
Scott Wood095b7122012-09-20 19:02:18 -050081 {
Prabhakar Kushwahaab4ab012013-04-16 13:27:59 +053082 arch/powerpc/cpu/mpc85xx/start.o (.bootpg)
Scott Wood095b7122012-09-20 19:02:18 -050083 }
Prabhakar Kushwahaa7eb72b2014-04-08 19:12:19 +053084#ifndef RESET_VECTOR_OFFSET
Scott Wood095b7122012-09-20 19:02:18 -050085#define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */
Prabhakar Kushwahaa7eb72b2014-04-08 19:12:19 +053086#endif
Scott Wood095b7122012-09-20 19:02:18 -050087#elif defined(CONFIG_FSL_ELBC)
88#define RESET_VECTOR_OFFSET 0xffc /* LBC has 4k sram */
89#else
90#error unknown NAND controller
91#endif
92 .resetvec ADDR(.text) + RESET_VECTOR_OFFSET : {
93 KEEP(*(.resetvec))
94 } = 0xffff
Ying Zhang0d4f5442013-05-20 14:07:23 +080095#endif
Scott Wood095b7122012-09-20 19:02:18 -050096
Prabhakar Kushwaha6e2b9a32014-04-08 19:12:31 +053097#ifndef CONFIG_SPL_SKIP_RELOCATE
Scott Wood095b7122012-09-20 19:02:18 -050098 /*
99 * Make sure that the bss segment isn't linked at 0x0, otherwise its
100 * address won't be updated during relocation fixups.
101 */
102 . |= 0x10;
103
Ying Zhang5ca62f22013-06-07 17:25:16 +0800104 . = ALIGN(4);
Scott Wood095b7122012-09-20 19:02:18 -0500105 __bss_start = .;
106 .bss : {
107 *(.sbss*)
108 *(.bss*)
109 }
Ying Zhang5ca62f22013-06-07 17:25:16 +0800110 . = ALIGN(4);
Simon Glassed70c8f2013-03-14 06:54:53 +0000111 __bss_end = .;
Prabhakar Kushwaha6e2b9a32014-04-08 19:12:31 +0530112#endif
Scott Wood095b7122012-09-20 19:02:18 -0500113}