blob: 0e0c63a14f325621d16bd92be08c913f4d011505 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Kumar Gala87ead052010-04-26 23:09:23 -05002/*
3 * Copyright 2010 Freescale Semiconductor, Inc.
Kumar Gala87ead052010-04-26 23:09:23 -05004 */
5
6#include <config.h>
7#include <common.h>
8#include <asm/io.h>
9#include <asm/immap_85xx.h>
10#include <asm/fsl_serdes.h>
11
12#define SRDS1_MAX_LANES 8
13
14static u32 serdes1_prtcl_map;
15
16static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
17 [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE},
18 [0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
19 [0x6] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1},
20 [0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE3, PCIE3},
21 [0xb] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1},
22 [0xc] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1},
23 [0xd] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1},
24 [0xe] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1},
25 [0xf] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1},
26};
27
28int is_serdes_configured(enum srds_prtcl prtcl)
29{
Hou Zhiqiangb435ae92016-08-02 19:03:22 +080030 if (!(serdes1_prtcl_map & (1 << NONE)))
31 fsl_serdes_init();
32
Kumar Gala87ead052010-04-26 23:09:23 -050033 return (1 << prtcl) & serdes1_prtcl_map;
34}
35
36void fsl_serdes_init(void)
37{
38 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
39 u32 pordevsr = in_be32(&gur->pordevsr);
40 u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
41 MPC85xx_PORDEVSR_IO_SEL_SHIFT;
42 int lane;
43
Hou Zhiqiangb435ae92016-08-02 19:03:22 +080044 if (serdes1_prtcl_map & (1 << NONE))
45 return;
46
Kumar Gala87ead052010-04-26 23:09:23 -050047 debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
48
Axel Linab95b092013-05-26 15:00:30 +080049 if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
Kumar Gala87ead052010-04-26 23:09:23 -050050 printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
51 return;
52 }
53
54 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
55 enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
56 serdes1_prtcl_map |= (1 << lane_prtcl);
57 }
58
59 if (!(pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
60 serdes1_prtcl_map |= (1 << SGMII_TSEC1);
61
62 if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
63 serdes1_prtcl_map |= (1 << SGMII_TSEC2);
64
65 if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
66 serdes1_prtcl_map |= (1 << SGMII_TSEC3);
67
68 if (!(pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
69 serdes1_prtcl_map |= (1 << SGMII_TSEC4);
Hou Zhiqiangb435ae92016-08-02 19:03:22 +080070
71 /* Set the first bit to indicate serdes has been initialized */
72 serdes1_prtcl_map |= (1 << NONE);
Kumar Gala87ead052010-04-26 23:09:23 -050073}