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git01.mediatek.com / filogic / uboot / dae027763982208ed1a420e3f24d35a504b23305 / . / arch / arm / dts / uniphier-common32.dtsi
blob: b0b2b57bb969aa8e88e970b4661daf26e5c532c6 [file] [log] [blame]
Masahiro Yamada3de725b2015-12-16 10:54:07 +0900[diff] [blame]1/*
2 * Device Tree Source commonly used by UniPhier ARM SoCs
3 *
4 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+ X11
7 */
8
9/include/ "skeleton.dtsi"
10
11/ {
Masahiro Yamada224e2f72016-02-02 21:11:33 +0900[diff] [blame]12 clocks {
13 refclk: ref {
14 #clock-cells = <0>;
15 compatible = "fixed-clock";
16 };
17 };
18
Masahiro Yamada3de725b2015-12-16 10:54:07 +0900[diff] [blame]19 soc: soc {
20 compatible = "simple-bus";
21 #address-cells = <1>;
22 #size-cells = <1>;
23 ranges;
24 interrupt-parent = <&intc>;
Masahiro Yamada1174603f2016-06-29 19:38:56 +0900[diff] [blame]25 u-boot,dm-pre-reloc;
Masahiro Yamada3de725b2015-12-16 10:54:07 +0900[diff] [blame]26
Masahiro Yamada3de725b2015-12-16 10:54:07 +0900[diff] [blame]27 serial0: serial@54006800 {
28 compatible = "socionext,uniphier-uart";
29 status = "disabled";
30 reg = <0x54006800 0x40>;
31 interrupts = <0 33 4>;
32 pinctrl-names = "default";
33 pinctrl-0 = <&pinctrl_uart0>;
34 clocks = <&uart_clk>;
35 };
36
37 serial1: serial@54006900 {
38 compatible = "socionext,uniphier-uart";
39 status = "disabled";
40 reg = <0x54006900 0x40>;
41 interrupts = <0 35 4>;
42 pinctrl-names = "default";
43 pinctrl-0 = <&pinctrl_uart1>;
44 clocks = <&uart_clk>;
45 };
46
47 serial2: serial@54006a00 {
48 compatible = "socionext,uniphier-uart";
49 status = "disabled";
50 reg = <0x54006a00 0x40>;
51 interrupts = <0 37 4>;
52 pinctrl-names = "default";
53 pinctrl-0 = <&pinctrl_uart2>;
54 clocks = <&uart_clk>;
55 };
56
57 serial3: serial@54006b00 {
58 compatible = "socionext,uniphier-uart";
59 status = "disabled";
60 reg = <0x54006b00 0x40>;
61 interrupts = <0 177 4>;
62 pinctrl-names = "default";
63 pinctrl-0 = <&pinctrl_uart3>;
64 clocks = <&uart_clk>;
65 };
66
Masahiro Yamada94c12bf2016-02-16 17:00:22 +0900[diff] [blame]67 system_bus: system-bus@58c00000 {
68 compatible = "socionext,uniphier-system-bus";
Masahiro Yamada1174603f2016-06-29 19:38:56 +0900[diff] [blame]69 status = "disabled";
Masahiro Yamada94c12bf2016-02-16 17:00:22 +0900[diff] [blame]70 reg = <0x58c00000 0x400>;
71 #address-cells = <2>;
72 #size-cells = <1>;
Masahiro Yamada1174603f2016-06-29 19:38:56 +0900[diff] [blame]73 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_system_bus>;
Masahiro Yamada94c12bf2016-02-16 17:00:22 +0900[diff] [blame]75 };
76
77 smpctrl@59800000 {
78 compatible = "socionext,uniphier-smpctrl";
79 reg = <0x59801000 0x400>;
Masahiro Yamada3de725b2015-12-16 10:54:07 +0900[diff] [blame]80 };
81
Masahiro Yamada1d5df7b2016-02-02 21:11:36 +0900[diff] [blame]82 mio: mioctrl@59810000 {
83 /* specify compatible in each SoC DTSI */
84 reg = <0x59810000 0x800>;
85 #clock-cells = <1>;
86 };
87
Masahiro Yamada80951832016-02-02 21:11:35 +0900[diff] [blame]88 peri: perictrl@59820000 {
89 /* specify compatible in each SoC DTSI */
90 reg = <0x59820000 0x200>;
91 #clock-cells = <1>;
92 };
93
Masahiro Yamada3de725b2015-12-16 10:54:07 +0900[diff] [blame]94 timer@60000200 {
95 compatible = "arm,cortex-a9-global-timer";
96 reg = <0x60000200 0x20>;
97 interrupts = <1 11 0x104>;
98 clocks = <&arm_timer_clk>;
99 };
100
101 timer@60000600 {
102 compatible = "arm,cortex-a9-twd-timer";
103 reg = <0x60000600 0x20>;
104 interrupts = <1 13 0x104>;
105 clocks = <&arm_timer_clk>;
106 };
107
108 intc: interrupt-controller@60001000 {
109 compatible = "arm,cortex-a9-gic";
110 reg = <0x60001000 0x1000>,
111 <0x60000100 0x100>;
112 #interrupt-cells = <3>;
113 interrupt-controller;
114 };
115
Masahiro Yamada1174603f2016-06-29 19:38:56 +0900[diff] [blame]116 soc-glue@5f800000 {
117 compatible = "simple-mfd", "syscon";
118 reg = <0x5f800000 0x2000>;
119 u-boot,dm-pre-reloc;
120
121 pinctrl: pinctrl {
122 /* specify compatible in each SoC DTSI */
123 u-boot,dm-pre-reloc;
124 };
Masahiro Yamada3de725b2015-12-16 10:54:07 +0900[diff] [blame]125 };
126
Masahiro Yamadae84513b2016-02-02 21:11:34 +0900[diff] [blame]127 sysctrl: sysctrl@61840000 {
128 /* specify compatible in each SoC DTSI */
129 reg = <0x61840000 0x4000>;
130 #clock-cells = <1>;
131 clock-names = "ref";
132 clocks = <&refclk>;
133 };
134
Masahiro Yamada3de725b2015-12-16 10:54:07 +0900[diff] [blame]135 nand: nand@68000000 {
136 compatible = "denali,denali-nand-dt";
Masahiro Yamada1174603f2016-06-29 19:38:56 +0900[diff] [blame]137 status = "disabled";
Masahiro Yamada3de725b2015-12-16 10:54:07 +0900[diff] [blame]138 reg-names = "nand_data", "denali_reg";
Masahiro Yamada1174603f2016-06-29 19:38:56 +0900[diff] [blame]139 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
140 interrupts = <0 65 4>;
141 pinctrl-names = "default";
142 pinctrl-0 = <&pinctrl_nand>;
Masahiro Yamada3de725b2015-12-16 10:54:07 +0900[diff] [blame]143 };
144 };
145};
146
147/include/ "uniphier-pinctrl.dtsi"