blob: 832815d80462871c0dc96372e2b6194b81f57785 [file] [log] [blame]
Beniamino Galvanid1037e42016-05-08 08:30:16 +02001/*
2 * Copyright (c) 2016 Andreas Färber
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include <dt-bindings/gpio/gpio.h>
44#include <dt-bindings/interrupt-controller/irq.h>
45#include <dt-bindings/interrupt-controller/arm-gic.h>
46
47/ {
48 compatible = "amlogic,meson-gxbb";
49 interrupt-parent = <&gic>;
50 #address-cells = <2>;
51 #size-cells = <2>;
52
53 cpus {
54 #address-cells = <0x2>;
55 #size-cells = <0x0>;
56
57 cpu0: cpu@0 {
58 device_type = "cpu";
59 compatible = "arm,cortex-a53", "arm,armv8";
60 reg = <0x0 0x0>;
61 enable-method = "psci";
62 };
63
64 cpu1: cpu@1 {
65 device_type = "cpu";
66 compatible = "arm,cortex-a53", "arm,armv8";
67 reg = <0x0 0x1>;
68 enable-method = "psci";
69 };
70
71 cpu2: cpu@2 {
72 device_type = "cpu";
73 compatible = "arm,cortex-a53", "arm,armv8";
74 reg = <0x0 0x2>;
75 enable-method = "psci";
76 };
77
78 cpu3: cpu@3 {
79 device_type = "cpu";
80 compatible = "arm,cortex-a53", "arm,armv8";
81 reg = <0x0 0x3>;
82 enable-method = "psci";
83 };
84 };
85
86 arm-pmu {
87 compatible = "arm,cortex-a53-pmu";
88 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
89 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
90 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
91 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
92 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
93 };
94
95 psci {
96 compatible = "arm,psci-0.2";
97 method = "smc";
98 };
99
100 timer {
101 compatible = "arm,armv8-timer";
102 interrupts = <GIC_PPI 13
103 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
104 <GIC_PPI 14
105 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
106 <GIC_PPI 11
107 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
108 <GIC_PPI 10
109 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>;
110 };
111
112 xtal: xtal-clk {
113 compatible = "fixed-clock";
114 clock-frequency = <24000000>;
115 clock-output-names = "xtal";
116 #clock-cells = <0>;
117 };
118
119 soc {
120 compatible = "simple-bus";
121 #address-cells = <2>;
122 #size-cells = <2>;
123 ranges;
124
125 cbus: cbus@c1100000 {
126 compatible = "simple-bus";
127 reg = <0x0 0xc1100000 0x0 0x100000>;
128 #address-cells = <2>;
129 #size-cells = <2>;
130 ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
131
132 uart_A: serial@84c0 {
133 compatible = "amlogic,meson-uart";
134 reg = <0x0 0x084c0 0x0 0x14>;
135 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
136 clocks = <&xtal>;
137 status = "disabled";
138 };
139 };
140
141 gic: interrupt-controller@c4301000 {
142 compatible = "arm,gic-400";
143 reg = <0x0 0xc4301000 0 0x1000>,
144 <0x0 0xc4302000 0 0x2000>,
145 <0x0 0xc4304000 0 0x2000>,
146 <0x0 0xc4306000 0 0x2000>;
147 interrupt-controller;
148 interrupts = <GIC_PPI 9
149 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
150 #interrupt-cells = <3>;
151 #address-cells = <0>;
152 };
153
154 aobus: aobus@c8100000 {
155 compatible = "simple-bus";
156 reg = <0x0 0xc8100000 0x0 0x100000>;
157 #address-cells = <2>;
158 #size-cells = <2>;
159 ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
160
161 uart_AO: serial@4c0 {
162 compatible = "amlogic,meson-uart";
163 reg = <0x0 0x004c0 0x0 0x14>;
164 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
165 clocks = <&xtal>;
166 status = "disabled";
167 };
168 };
169
170 apb: apb@d0000000 {
171 compatible = "simple-bus";
172 reg = <0x0 0xd0000000 0x0 0x200000>;
173 #address-cells = <2>;
174 #size-cells = <2>;
175 ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
176 };
177 };
178};