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git01.mediatek.com / filogic / uboot / dae027763982208ed1a420e3f24d35a504b23305 / . / arch / arm / dts / k2g.dtsi
blob: 00cd492973366e0c0f6108486148cc645c7209fc [file] [log] [blame]
Lokesh Vutlae8e92b82015-09-19 16:26:55 +0530[diff] [blame]1/*
2 * Copyright 2014 Texas Instruments, Inc.
3 *
4 * Keystone 2 Galileo soc device tree
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12#include "skeleton.dtsi"
13
14/ {
15 model = "Texas Instruments Keystone 2 SoC";
16 #address-cells = <1>;
17 #size-cells = <1>;
18 interrupt-parent = <&gic>;
19
20 aliases {
21 serial0 = &uart0;
Vignesh Rcefb8f32016-07-06 09:59:05 +0530[diff] [blame]22 spi0 = &spi0;
23 spi1 = &spi1;
24 spi2 = &spi2;
25 spi3 = &spi3;
Vignesh R9b9f0f82016-07-06 10:20:57 +0530[diff] [blame]26 spi4 = &qspi;
Lokesh Vutlae8e92b82015-09-19 16:26:55 +0530[diff] [blame]27 };
28
29 memory {
30 device_type = "memory";
31 reg = <0x80000000 0x80000000>;
32 };
33
34 cpus {
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 interrupt-parent = <&gic>;
39
40 cpu@0 {
41 compatible = "arm,cortex-a15";
42 device_type = "cpu";
43 reg = <0>;
44 };
45 };
46
47 gic: interrupt-controller {
48 compatible = "arm,cortex-a15-gic";
49 #interrupt-cells = <3>;
50 interrupt-controller;
51 reg = <0x0 0x02561000 0x0 0x1000>,
52 <0x0 0x02562000 0x0 0x2000>,
53 <0x0 0x02564000 0x0 0x1000>,
54 <0x0 0x02566000 0x0 0x2000>;
55 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
56 IRQ_TYPE_LEVEL_HIGH)>;
57 };
58
59 soc {
60 #address-cells = <1>;
61 #size-cells = <1>;
62 compatible = "ti,keystone","simple-bus";
63 interrupt-parent = <&gic>;
64 ranges;
65
66 uart0: serial@02530c00 {
67 compatible = "ns16550a";
68 current-speed = <115200>;
69 reg-shift = <2>;
70 reg-io-width = <4>;
71 reg = <0x02530c00 0x100>;
72 clock-names = "uart";
73 interrupts = <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>;
74 };
75
Mugunthan V N3784cc22016-02-02 15:51:37 +0530[diff] [blame]76 mdio: mdio@4200f00 {
77 compatible = "ti,keystone_mdio", "ti,davinci_mdio";
78 #address-cells = <1>;
79 #size-cells = <0>;
80 /* power-domains = <&k2g_pds K2G_DEV_NSS0>; */
81 /* clocks = <&k2g_clks K2G_DEV_NSS0 K2G_DEV_NSS_ESW_CLK>; */
82 clock-names = "fck";
83 reg = <0x04200f00 0x100>;
84 status = "disabled";
85 bus_freq = <2500000>;
86 };
87
Vignesh R9b9f0f82016-07-06 10:20:57 +0530[diff] [blame]88 qspi: qspi@2940000 {
89 compatible = "cadence,qspi";
90 #address-cells = <1>;
91 #size-cells = <0>;
92 reg = <0x02940000 0x1000>,
93 <0x24000000 0x4000000>;
94 interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
95 num-cs = <4>;
96 fifo-depth = <256>;
97 sram-size = <256>;
98 status = "disabled";
99 };
100
Mugunthan V N3784cc22016-02-02 15:51:37 +0530[diff] [blame]101 #include "k2g-netcp.dtsi"
Nishanth Menon715137c2016-02-25 12:53:46 -0600[diff] [blame]102
103 pmmc: pmmc@2900000 {
104 compatible = "ti,power-processor";
105 reg = <0x02900000 0x40000>;
106 ti,lpsc_module = <1>;
107 };
108
Vignesh Rcefb8f32016-07-06 09:59:05 +0530[diff] [blame]109 spi0: spi@21805400 {
110 compatible = "ti,keystone-spi", "ti,dm6441-spi";
111 reg = <0x21805400 0x200>;
112 num-cs = <4>;
113 ti,davinci-spi-intr-line = <0>;
114 interrupts = <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>;
115 #address-cells = <1>;
116 #size-cells = <0>;
117 status = "disabled";
118 };
119
120 spi1: spi@21805800 {
121 compatible = "ti,keystone-spi", "ti,dm6441-spi";
122 reg = <0x21805800 0x200>;
123 num-cs = <4>;
124 ti,davinci-spi-intr-line = <0>;
125 interrupts = <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>;
126 #address-cells = <1>;
127 #size-cells = <0>;
128 status = "disabled";
129 };
130
131 spi2: spi@21805c00 {
132 compatible = "ti,keystone-spi", "ti,dm6441-spi";
133 reg = <0x21805C00 0x200>;
134 num-cs = <4>;
135 ti,davinci-spi-intr-line = <0>;
136 interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
137 #address-cells = <1>;
138 #size-cells = <0>;
139 status = "disabled";
140 };
141
142 spi3: spi@21806000 {
143 compatible = "ti,keystone-spi", "ti,dm6441-spi";
144 reg = <0x21806000 0x200>;
145 num-cs = <4>;
146 ti,davinci-spi-intr-line = <0>;
147 interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>;
148 #address-cells = <1>;
149 #size-cells = <0>;
150 status = "disabled";
151 };
Lokesh Vutlae8e92b82015-09-19 16:26:55 +0530[diff] [blame]152 };
153};