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git01.mediatek.com / filogic / uboot / dad9751087d16f3ff6b14965e0b58093fcd9bf34 / . / arch / mips / dts / pic32mzda.dtsi
blob: 43cd7cf3047b6e71fbbb9c7395382b63a464f04d [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Purna Chandra Mandal5c2dcd22016-01-28 15:30:16 +0530[diff] [blame]2/*
3 * Copyright 2015 Microchip Technology, Inc.
4 * Purna Chandra Mandal, <purna.mandal@microchip.com>
Purna Chandra Mandal5c2dcd22016-01-28 15:30:16 +0530[diff] [blame]5 */
6
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/clock/microchip,clock.h>
9#include <dt-bindings/gpio/gpio.h>
10#include "skeleton.dtsi"
11
12/ {
13 compatible = "microchip,pic32mzda", "microchip,pic32mz";
14
15 aliases {
16 gpio0 = &gpioA;
17 gpio1 = &gpioB;
18 gpio2 = &gpioC;
19 gpio3 = &gpioD;
20 gpio4 = &gpioE;
21 gpio5 = &gpioF;
22 gpio6 = &gpioG;
23 gpio7 = &gpioH;
24 gpio8 = &gpioJ;
25 gpio9 = &gpioK;
26 };
27
28 cpus {
John Robertson93cb0a12020-09-01 04:14:56 +0000[diff] [blame]29 #address-cells = <1>;
30 #size-cells = <0>;
31
Purna Chandra Mandal5c2dcd22016-01-28 15:30:16 +0530[diff] [blame]32 cpu@0 {
33 compatible = "mips,mips14kc";
John Robertson93cb0a12020-09-01 04:14:56 +0000[diff] [blame]34 device-type = "cpu";
35 reg = <0>;
Purna Chandra Mandal5c2dcd22016-01-28 15:30:16 +0530[diff] [blame]36 };
37 };
38
39 clock: clk@1f801200 {
40 compatible = "microchip,pic32mzda-clk";
41 reg = <0x1f801200 0x1000>;
42 #clock-cells = <1>;
43 };
44
45 uart1: serial@1f822000 {
46 compatible = "microchip,pic32mzda-uart";
47 reg = <0x1f822000 0x50>;
John Robertson93cb0a12020-09-01 04:14:56 +0000[diff] [blame]48 interrupt-parent = <&evic>;
Purna Chandra Mandal5c2dcd22016-01-28 15:30:16 +0530[diff] [blame]49 interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
50 status = "disabled";
51 clocks = <&clock PB2CLK>;
52 };
53
54 uart2: serial@1f822200 {
55 compatible = "microchip,pic32mzda-uart";
56 reg = <0x1f822200 0x50>;
John Robertson93cb0a12020-09-01 04:14:56 +0000[diff] [blame]57 interrupt-parent = <&evic>;
Purna Chandra Mandal5c2dcd22016-01-28 15:30:16 +0530[diff] [blame]58 interrupts = <145 IRQ_TYPE_LEVEL_HIGH>;
59 clocks = <&clock PB2CLK>;
60 status = "disabled";
61 };
62
63 uart6: serial@1f822a00 {
64 compatible = "microchip,pic32mzda-uart";
65 reg = <0x1f822a00 0x50>;
John Robertson93cb0a12020-09-01 04:14:56 +0000[diff] [blame]66 interrupt-parent = <&evic>;
Purna Chandra Mandal5c2dcd22016-01-28 15:30:16 +0530[diff] [blame]67 interrupts = <188 IRQ_TYPE_LEVEL_HIGH>;
68 clocks = <&clock PB2CLK>;
69 status = "disabled";
70 };
71
72 evic: interrupt-controller@1f810000 {
73 compatible = "microchip,pic32mzda-evic";
74 interrupt-controller;
75 #interrupt-cells = <2>;
76 reg = <0x1f810000 0x1000>;
77 };
78
79 pinctrl: pinctrl@1f801400 {
John Robertsona8e58362020-09-01 18:02:13 +0000[diff] [blame]80 #address-cells = <1>;
81 #size-cells = <1>;
Purna Chandra Mandal5c2dcd22016-01-28 15:30:16 +0530[diff] [blame]82 compatible = "microchip,pic32mzda-pinctrl";
83 reg = <0x1f801400 0x100>, /* in */
84 <0x1f801500 0x200>, /* out */
85 <0x1f860000 0xa00>; /* port */
86 reg-names = "ppsin","ppsout","port";
87 status = "disabled";
88
John Robertsona8e58362020-09-01 18:02:13 +0000[diff] [blame]89 gpioA: gpio0@1f860000 {
Purna Chandra Mandal5c2dcd22016-01-28 15:30:16 +0530[diff] [blame]90 compatible = "microchip,pic32mzda-gpio";
John Robertsona8e58362020-09-01 18:02:13 +0000[diff] [blame]91 reg = <0x1f860000 0xe0>;
Purna Chandra Mandal5c2dcd22016-01-28 15:30:16 +0530[diff] [blame]92 gpio-controller;
93 #gpio-cells = <2>;
94 };
95
John Robertsona8e58362020-09-01 18:02:13 +0000[diff] [blame]96 gpioB: gpio1@1f860100 {
Purna Chandra Mandal5c2dcd22016-01-28 15:30:16 +0530[diff] [blame]97 compatible = "microchip,pic32mzda-gpio";
John Robertsona8e58362020-09-01 18:02:13 +0000[diff] [blame]98 reg = <0x1f860100 0xe0>;
Purna Chandra Mandal5c2dcd22016-01-28 15:30:16 +0530[diff] [blame]99 gpio-controller;
100 #gpio-cells = <2>;
101 };
102
John Robertsona8e58362020-09-01 18:02:13 +0000[diff] [blame]103 gpioC: gpio2@1f860200 {
Purna Chandra Mandal5c2dcd22016-01-28 15:30:16 +0530[diff] [blame]104 compatible = "microchip,pic32mzda-gpio";
John Robertsona8e58362020-09-01 18:02:13 +0000[diff] [blame]105 reg = <0x1f860200 0xe0>;
Purna Chandra Mandal5c2dcd22016-01-28 15:30:16 +0530[diff] [blame]106 gpio-controller;
107 #gpio-cells = <2>;
108 };
109
John Robertsona8e58362020-09-01 18:02:13 +0000[diff] [blame]110 gpioD: gpio3@1f860300 {
Purna Chandra Mandal5c2dcd22016-01-28 15:30:16 +0530[diff] [blame]111 compatible = "microchip,pic32mzda-gpio";
John Robertsona8e58362020-09-01 18:02:13 +0000[diff] [blame]112 reg = <0x1f860300 0xe0>;
Purna Chandra Mandal5c2dcd22016-01-28 15:30:16 +0530[diff] [blame]113 gpio-controller;
114 #gpio-cells = <2>;
115 };
116
John Robertsona8e58362020-09-01 18:02:13 +0000[diff] [blame]117 gpioE: gpio4@1f860400 {
Purna Chandra Mandal5c2dcd22016-01-28 15:30:16 +0530[diff] [blame]118 compatible = "microchip,pic32mzda-gpio";
John Robertsona8e58362020-09-01 18:02:13 +0000[diff] [blame]119 reg = <0x1f860400 0xe0>;
Purna Chandra Mandal5c2dcd22016-01-28 15:30:16 +0530[diff] [blame]120 gpio-controller;
121 #gpio-cells = <2>;
122 };
123
John Robertsona8e58362020-09-01 18:02:13 +0000[diff] [blame]124 gpioF: gpio5@1f860500 {
Purna Chandra Mandal5c2dcd22016-01-28 15:30:16 +0530[diff] [blame]125 compatible = "microchip,pic32mzda-gpio";
John Robertsona8e58362020-09-01 18:02:13 +0000[diff] [blame]126 reg = <0x1f860500 0xe0>;
Purna Chandra Mandal5c2dcd22016-01-28 15:30:16 +0530[diff] [blame]127 gpio-controller;
128 #gpio-cells = <2>;
129 };
130
John Robertsona8e58362020-09-01 18:02:13 +0000[diff] [blame]131 gpioG: gpio6@1f860600 {
Purna Chandra Mandal5c2dcd22016-01-28 15:30:16 +0530[diff] [blame]132 compatible = "microchip,pic32mzda-gpio";
John Robertsona8e58362020-09-01 18:02:13 +0000[diff] [blame]133 reg = <0x1f860600 0xe0>;
Purna Chandra Mandal5c2dcd22016-01-28 15:30:16 +0530[diff] [blame]134 gpio-controller;
135 #gpio-cells = <2>;
136 };
137
John Robertsona8e58362020-09-01 18:02:13 +0000[diff] [blame]138 gpioH: gpio7@1f860700 {
Purna Chandra Mandal5c2dcd22016-01-28 15:30:16 +0530[diff] [blame]139 compatible = "microchip,pic32mzda-gpio";
John Robertsona8e58362020-09-01 18:02:13 +0000[diff] [blame]140 reg = <0x1f860700 0xe0>;
Purna Chandra Mandal5c2dcd22016-01-28 15:30:16 +0530[diff] [blame]141 gpio-controller;
142 #gpio-cells = <2>;
143 };
144
John Robertsona11b4db2020-09-01 18:02:20 +0000[diff] [blame]145 gpioJ: gpio9@1f860800 {
Purna Chandra Mandal5c2dcd22016-01-28 15:30:16 +0530[diff] [blame]146 compatible = "microchip,pic32mzda-gpio";
John Robertsona8e58362020-09-01 18:02:13 +0000[diff] [blame]147 reg = <0x1f860800 0xe0>;
Purna Chandra Mandal5c2dcd22016-01-28 15:30:16 +0530[diff] [blame]148 gpio-controller;
149 #gpio-cells = <2>;
150 };
151
John Robertsona11b4db2020-09-01 18:02:20 +0000[diff] [blame]152 gpioK: gpio10@1f860900 {
Purna Chandra Mandal5c2dcd22016-01-28 15:30:16 +0530[diff] [blame]153 compatible = "microchip,pic32mzda-gpio";
John Robertsona8e58362020-09-01 18:02:13 +0000[diff] [blame]154 reg = <0x1f860900 0xe0>;
Purna Chandra Mandal5c2dcd22016-01-28 15:30:16 +0530[diff] [blame]155 gpio-controller;
156 #gpio-cells = <2>;
157 };
158 };
Purna Chandra Mandal85491f52016-01-28 15:30:19 +0530[diff] [blame]159
160 sdhci: sdhci@1f8ec000 {
161 compatible = "microchip,pic32mzda-sdhci";
162 reg = <0x1f8ec000 0x100>;
John Robertson93cb0a12020-09-01 04:14:56 +0000[diff] [blame]163 interrupt-parent = <&evic>;
Purna Chandra Mandal85491f52016-01-28 15:30:19 +0530[diff] [blame]164 interrupts = <191 IRQ_TYPE_LEVEL_HIGH>;
165 clocks = <&clock REF4CLK>, <&clock PB5CLK>;
166 clock-names = "base_clk", "sys_clk";
167 clock-freq-min-max = <25000000>,<25000000>;
168 bus-width = <4>;
169 status = "disabled";
170 };
Purna Chandra Mandald3191482016-01-28 15:30:22 +0530[diff] [blame]171
172 ethernet: ethernet@1f882000 {
173 compatible = "microchip,pic32mzda-eth";
174 reg = <0x1f882000 0x1000>;
John Robertson93cb0a12020-09-01 04:14:56 +0000[diff] [blame]175 interrupt-parent = <&evic>;
Purna Chandra Mandald3191482016-01-28 15:30:22 +0530[diff] [blame]176 interrupts = <153 IRQ_TYPE_LEVEL_HIGH>;
177 clocks = <&clock PB5CLK>;
178 status = "disabled";
179 #address-cells = <1>;
180 #size-cells = <0>;
181 };
Purna Chandra Mandala8b8f7b2016-03-21 13:05:43 +0530[diff] [blame]182
183 usb: musb@1f8e3000 {
184 compatible = "microchip,pic32mzda-usb";
185 reg = <0x1f8e3000 0x1000>,
186 <0x1f884000 0x1000>;
187 reg-names = "mc", "control";
John Robertson93cb0a12020-09-01 04:14:56 +0000[diff] [blame]188 interrupt-parent = <&evic>;
Purna Chandra Mandala8b8f7b2016-03-21 13:05:43 +0530[diff] [blame]189 interrupts = <132 IRQ_TYPE_EDGE_RISING>,
190 <133 IRQ_TYPE_LEVEL_HIGH>;
191 clocks = <&clock PB5CLK>;
192 clock-names = "usb_clk";
193 status = "disabled";
194 };
Purna Chandra Mandal5c2dcd22016-01-28 15:30:16 +0530[diff] [blame]195};