Wolfgang Denk | 52744b4 | 2013-07-28 22:12:45 +0200 | [diff] [blame] | 1 | /* |
Wolfgang Denk | 815c967 | 2013-09-17 11:24:06 +0200 | [diff] [blame] | 2 | * SPDX-License-Identifier: GPL-2.0 IBM-pibs |
Wolfgang Denk | 52744b4 | 2013-07-28 22:12:45 +0200 | [diff] [blame] | 3 | */ |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 4 | |
| 5 | /*----------------------------------------------------------------------------- */ |
| 6 | /* Function: ext_bus_cntlr_init */ |
| 7 | /* Description: Initializes the External Bus Controller for the external */ |
| 8 | /* peripherals. IMPORTANT: For pass1 this code must run from */ |
| 9 | /* cache since you can not reliably change a peripheral banks */ |
| 10 | /* timing register (pbxap) while running code from that bank. */ |
| 11 | /* For ex., since we are running from ROM on bank 0, we can NOT */ |
| 12 | /* execute the code that modifies bank 0 timings from ROM, so */ |
| 13 | /* we run it from cache. */ |
| 14 | /* Bank 0 - Flash and SRAM */ |
| 15 | /* Bank 1 - NVRAM/RTC */ |
| 16 | /* Bank 2 - Keyboard/Mouse controller */ |
| 17 | /* Bank 3 - IR controller */ |
| 18 | /* Bank 4 - not used */ |
| 19 | /* Bank 5 - not used */ |
| 20 | /* Bank 6 - not used */ |
| 21 | /* Bank 7 - FPGA registers */ |
| 22 | /*-----------------------------------------------------------------------------#include <config.h> */ |
Stefan Roese | 247e9d7 | 2010-09-09 19:18:00 +0200 | [diff] [blame] | 23 | #include <asm/ppc4xx.h> |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 24 | |
| 25 | #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ |
| 26 | |
| 27 | #include <ppc_asm.tmpl> |
| 28 | #include <ppc_defs.h> |
| 29 | |
| 30 | #include <asm/cache.h> |
| 31 | #include <asm/mmu.h> |
| 32 | |
| 33 | /* CRAY - L1: only nominally a 'walnut', since ext.Bus.Cntlr is all empty */ |
| 34 | /* except for #1 which we use for DMA'ing to IOCA-like things, so the */ |
| 35 | /* control registers to set that up are determined by what we've */ |
| 36 | /* empirically discovered work there. */ |
| 37 | |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 38 | .globl ext_bus_cntlr_init |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 39 | ext_bus_cntlr_init: |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 40 | mflr r4 /* save link register */ |
| 41 | bl ..getAddr |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 42 | ..getAddr: |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 43 | mflr r3 /* get address of ..getAddr */ |
| 44 | mtlr r4 /* restore link register */ |
| 45 | addi r4,0,14 /* set ctr to 10; used to prefetch */ |
| 46 | mtctr r4 /* 10 cache lines to fit this function */ |
| 47 | /* in cache (gives us 8x10=80 instrctns) */ |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 48 | ..ebcloop: |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 49 | icbt r0,r3 /* prefetch cache line for addr in r3 */ |
| 50 | addi r3,r3,32 /* move to next cache line */ |
| 51 | bdnz ..ebcloop /* continue for 10 cache lines */ |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 52 | |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 53 | /*------------------------------------------------------------------- */ |
| 54 | /* Delay to ensure all accesses to ROM are complete before changing */ |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 55 | /* bank 0 timings. 200usec should be enough. */ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 56 | /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */ |
| 57 | /*------------------------------------------------------------------- */ |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 58 | addis r3,0,0x0 |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 59 | ori r3,r3,0xA000 /* ensure 200usec have passed since reset */ |
| 60 | mtctr r3 |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 61 | ..spinlp: |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 62 | bdnz ..spinlp /* spin loop */ |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 63 | |
| 64 | |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 65 | /*---------------------------------------------------------------------- */ |
| 66 | /* Peripheral Bank 0 (Flash) initialization */ |
| 67 | /*---------------------------------------------------------------------- */ |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 68 | /* 0x7F8FFE80 slowest boot */ |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 69 | addi r4,0,PB1AP |
| 70 | mtdcr EBC0_CFGADDR,r4 |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 71 | addis r4,0,0x9B01 |
| 72 | ori r4,r4,0x5480 |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 73 | mtdcr EBC0_CFGDATA,r4 |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 74 | |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 75 | addi r4,0,PB0CR |
| 76 | mtdcr EBC0_CFGADDR,r4 |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 77 | addis r4,0,0xFFC5 /* BAS=0xFFC,BS=0x4(4MB),BU=0x3(R/W), */ |
| 78 | ori r4,r4,0x8000 /* BW=0x0( 8 bits) */ |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 79 | mtdcr EBC0_CFGDATA,r4 |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 80 | |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 81 | blr |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 82 | |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 83 | /*---------------------------------------------------------------------- */ |
| 84 | /* Peripheral Bank 1 (NVRAM/RTC) initialization */ |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 85 | /* CRAY:the L1 has NOT this bank, it is tied to SV2/IOCA/etc/ instead */ |
| 86 | /* and we do DMA on it. The ConfigurationRegister part is threfore */ |
| 87 | /* almost arbitrary, except that our linux driver needs to know the */ |
| 88 | /* address, but it can query, it.. */ |
| 89 | /* */ |
| 90 | /* The AccessParameter is CRITICAL, */ |
| 91 | /* thouch, since it needs to agree with the electrical timings on the */ |
| 92 | /* IOCA parallel interface. That value is: 0x0185,4380 */ |
| 93 | /* BurstModeEnable BME=0 */ |
| 94 | /* TransferWait TWT=3 */ |
| 95 | /* ChipSelectOnTiming CSN=1 */ |
| 96 | /* OutputEnableOnTimimg OEN=1 */ |
| 97 | /* WriteByteEnableOnTiming WBN=1 */ |
| 98 | /* WriteByteEnableOffTiming WBF=0 */ |
| 99 | /* TransferHold TH=1 */ |
| 100 | /* ReadyEnable RE=1 */ |
| 101 | /* SampleOnReady SOR=1 */ |
| 102 | /* ByteEnableMode BEM=0 */ |
| 103 | /* ParityEnable PEN=0 */ |
| 104 | /* all reserved bits=0 */ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 105 | /*---------------------------------------------------------------------- */ |
| 106 | /*---------------------------------------------------------------------- */ |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 107 | addi r4,0,PB1AP |
| 108 | mtdcr EBC0_CFGADDR,r4 |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 109 | addis r4,0,0x0185 /* hiword */ |
| 110 | ori r4,r4,0x4380 /* loword */ |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 111 | mtdcr EBC0_CFGDATA,r4 |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 112 | |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 113 | addi r4,0,PB1CR |
| 114 | mtdcr EBC0_CFGADDR,r4 |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 115 | addis r4,0,0xF001 /* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W), */ |
| 116 | ori r4,r4,0x8000 /* BW=0x0( 8 bits) */ |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 117 | mtdcr EBC0_CFGDATA,r4 |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 118 | |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 119 | blr |