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git01.mediatek.com / filogic / uboot / dac4073e2a24b8238f982efaa75c9cecfe0b57b0 / . / board / renesas / porter / qos.c
blob: bca54f7f74c6e959ae1ecb89c5b713d9d0a27099 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
Vladimir Barinov2f8c00e2015-02-14 01:06:13 +0300[diff] [blame]2/*
3 * board/renesas/porter/qos.c
4 *
5 * Copyright (C) 2015 Renesas Electronics Corporation
6 * Copyright (C) 2015 Cogent Embedded, Inc.
7 *
Vladimir Barinov2f8c00e2015-02-14 01:06:13 +0300[diff] [blame]8 */
9
10#include <common.h>
11#include <asm/processor.h>
12#include <asm/mach-types.h>
13#include <asm/io.h>
14#include <asm/arch/rmobile.h>
15
16/* QoS version 0.240 for ES1 and version 0.334 for ES2 */
Nobuhiro Iwamatsu7c112732015-10-10 05:58:28 +0900[diff] [blame]17#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
Vladimir Barinov2f8c00e2015-02-14 01:06:13 +0300[diff] [blame]18enum {
19 DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
20 DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
21 DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14,
22 DBSC3_15,
23 DBSC3_NR,
24};
25
26static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = {
27 [DBSC3_00] = DBSC3_0_QOS_R0_BASE,
28 [DBSC3_01] = DBSC3_0_QOS_R1_BASE,
29 [DBSC3_02] = DBSC3_0_QOS_R2_BASE,
30 [DBSC3_03] = DBSC3_0_QOS_R3_BASE,
31 [DBSC3_04] = DBSC3_0_QOS_R4_BASE,
32 [DBSC3_05] = DBSC3_0_QOS_R5_BASE,
33 [DBSC3_06] = DBSC3_0_QOS_R6_BASE,
34 [DBSC3_07] = DBSC3_0_QOS_R7_BASE,
35 [DBSC3_08] = DBSC3_0_QOS_R8_BASE,
36 [DBSC3_09] = DBSC3_0_QOS_R9_BASE,
37 [DBSC3_10] = DBSC3_0_QOS_R10_BASE,
38 [DBSC3_11] = DBSC3_0_QOS_R11_BASE,
39 [DBSC3_12] = DBSC3_0_QOS_R12_BASE,
40 [DBSC3_13] = DBSC3_0_QOS_R13_BASE,
41 [DBSC3_14] = DBSC3_0_QOS_R14_BASE,
42 [DBSC3_15] = DBSC3_0_QOS_R15_BASE,
43};
44
45static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = {
46 [DBSC3_00] = DBSC3_0_QOS_W0_BASE,
47 [DBSC3_01] = DBSC3_0_QOS_W1_BASE,
48 [DBSC3_02] = DBSC3_0_QOS_W2_BASE,
49 [DBSC3_03] = DBSC3_0_QOS_W3_BASE,
50 [DBSC3_04] = DBSC3_0_QOS_W4_BASE,
51 [DBSC3_05] = DBSC3_0_QOS_W5_BASE,
52 [DBSC3_06] = DBSC3_0_QOS_W6_BASE,
53 [DBSC3_07] = DBSC3_0_QOS_W7_BASE,
54 [DBSC3_08] = DBSC3_0_QOS_W8_BASE,
55 [DBSC3_09] = DBSC3_0_QOS_W9_BASE,
56 [DBSC3_10] = DBSC3_0_QOS_W10_BASE,
57 [DBSC3_11] = DBSC3_0_QOS_W11_BASE,
58 [DBSC3_12] = DBSC3_0_QOS_W12_BASE,
59 [DBSC3_13] = DBSC3_0_QOS_W13_BASE,
60 [DBSC3_14] = DBSC3_0_QOS_W14_BASE,
61 [DBSC3_15] = DBSC3_0_QOS_W15_BASE,
62};
63
64static u32 dbsc3_1_r_qos_addr[DBSC3_NR] = {
65 [DBSC3_00] = DBSC3_1_QOS_R0_BASE,
66 [DBSC3_01] = DBSC3_1_QOS_R1_BASE,
67 [DBSC3_02] = DBSC3_1_QOS_R2_BASE,
68 [DBSC3_03] = DBSC3_1_QOS_R3_BASE,
69 [DBSC3_04] = DBSC3_1_QOS_R4_BASE,
70 [DBSC3_05] = DBSC3_1_QOS_R5_BASE,
71 [DBSC3_06] = DBSC3_1_QOS_R6_BASE,
72 [DBSC3_07] = DBSC3_1_QOS_R7_BASE,
73 [DBSC3_08] = DBSC3_1_QOS_R8_BASE,
74 [DBSC3_09] = DBSC3_1_QOS_R9_BASE,
75 [DBSC3_10] = DBSC3_1_QOS_R10_BASE,
76 [DBSC3_11] = DBSC3_1_QOS_R11_BASE,
77 [DBSC3_12] = DBSC3_1_QOS_R12_BASE,
78 [DBSC3_13] = DBSC3_1_QOS_R13_BASE,
79 [DBSC3_14] = DBSC3_1_QOS_R14_BASE,
80 [DBSC3_15] = DBSC3_1_QOS_R15_BASE,
81};
82
83static u32 dbsc3_1_w_qos_addr[DBSC3_NR] = {
84 [DBSC3_00] = DBSC3_1_QOS_W0_BASE,
85 [DBSC3_01] = DBSC3_1_QOS_W1_BASE,
86 [DBSC3_02] = DBSC3_1_QOS_W2_BASE,
87 [DBSC3_03] = DBSC3_1_QOS_W3_BASE,
88 [DBSC3_04] = DBSC3_1_QOS_W4_BASE,
89 [DBSC3_05] = DBSC3_1_QOS_W5_BASE,
90 [DBSC3_06] = DBSC3_1_QOS_W6_BASE,
91 [DBSC3_07] = DBSC3_1_QOS_W7_BASE,
92 [DBSC3_08] = DBSC3_1_QOS_W8_BASE,
93 [DBSC3_09] = DBSC3_1_QOS_W9_BASE,
94 [DBSC3_10] = DBSC3_1_QOS_W10_BASE,
95 [DBSC3_11] = DBSC3_1_QOS_W11_BASE,
96 [DBSC3_12] = DBSC3_1_QOS_W12_BASE,
97 [DBSC3_13] = DBSC3_1_QOS_W13_BASE,
98 [DBSC3_14] = DBSC3_1_QOS_W14_BASE,
99 [DBSC3_15] = DBSC3_1_QOS_W15_BASE,
100};
101
102void qos_init(void)
103{
104 int i;
105 struct rcar_s3c *s3c;
106 struct rcar_s3c_qos *s3c_qos;
107 struct rcar_dbsc3_qos *qos_addr;
108 struct rcar_mxi *mxi;
109 struct rcar_mxi_qos *mxi_qos;
110 struct rcar_axi_qos *axi_qos;
111
112 /* DBSC DBADJ2 */
113 writel(0x20042004, DBSC3_0_DBADJ2);
114 writel(0x20042004, DBSC3_1_DBADJ2);
115
116 /* S3C -QoS */
117 s3c = (struct rcar_s3c *)S3C_BASE;
118 if (IS_R8A7791_ES2()) {
119 /* Linear All mode */
120 /* writel(0x00000000, &s3c->s3cadsplcr); */
121 /* Linear Linear 0x7000 to 0x7800 mode */
122 writel(0x00BF1B0C, &s3c->s3cadsplcr);
123 /* Split Linear 0x6800 t 0x7000 mode */
124 /* writel(0x00DF1B0C, &s3c->s3cadsplcr); */
125 /* Ssplit All mode */
126 /* writel(0x00FF1B0C, &s3c->s3cadsplcr); */
127 writel(0x1F0B0908, &s3c->s3crorr);
128 writel(0x1F0C0A08, &s3c->s3cworr);
129 } else {
130 writel(0x00FF1B1D, &s3c->s3cadsplcr);
131 writel(0x1F0D0C0C, &s3c->s3crorr);
132 writel(0x1F0D0C0A, &s3c->s3cworr);
133 }
134 /* QoS Control Registers */
135 s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
136 writel(0x00890089, &s3c_qos->s3cqos0);
137 writel(0x20960010, &s3c_qos->s3cqos1);
138 writel(0x20302030, &s3c_qos->s3cqos2);
139 writel(0x20AA2200, &s3c_qos->s3cqos3);
140 writel(0x00002032, &s3c_qos->s3cqos4);
141 writel(0x20960010, &s3c_qos->s3cqos5);
142 writel(0x20302030, &s3c_qos->s3cqos6);
143 writel(0x20AA2200, &s3c_qos->s3cqos7);
144 writel(0x00002032, &s3c_qos->s3cqos8);
145
146 s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
147 writel(0x00890089, &s3c_qos->s3cqos0);
148 writel(0x20960010, &s3c_qos->s3cqos1);
149 writel(0x20302030, &s3c_qos->s3cqos2);
150 writel(0x20AA2200, &s3c_qos->s3cqos3);
151 writel(0x00002032, &s3c_qos->s3cqos4);
152 writel(0x20960010, &s3c_qos->s3cqos5);
153 writel(0x20302030, &s3c_qos->s3cqos6);
154 writel(0x20AA2200, &s3c_qos->s3cqos7);
155 writel(0x00002032, &s3c_qos->s3cqos8);
156
157 s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
158 writel(0x00820082, &s3c_qos->s3cqos0);
159 writel(0x20960020, &s3c_qos->s3cqos1);
160 writel(0x20302030, &s3c_qos->s3cqos2);
161 writel(0x20AA20DC, &s3c_qos->s3cqos3);
162 writel(0x00002032, &s3c_qos->s3cqos4);
163 writel(0x20960020, &s3c_qos->s3cqos5);
164 writel(0x20302030, &s3c_qos->s3cqos6);
165 writel(0x20AA20DC, &s3c_qos->s3cqos7);
166 writel(0x00002032, &s3c_qos->s3cqos8);
167
168 s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
169 writel(0x00820082, &s3c_qos->s3cqos0);
170 writel(0x20960020, &s3c_qos->s3cqos1);
171 writel(0x20302030, &s3c_qos->s3cqos2);
172 writel(0x20AA20FA, &s3c_qos->s3cqos3);
173 writel(0x00002032, &s3c_qos->s3cqos4);
174 writel(0x20960020, &s3c_qos->s3cqos5);
175 writel(0x20302030, &s3c_qos->s3cqos6);
176 writel(0x20AA20FA, &s3c_qos->s3cqos7);
177 writel(0x00002032, &s3c_qos->s3cqos8);
178
179 /* DBSC -QoS */
180 /* DBSC0 - Read */
181 for (i = DBSC3_00; i < DBSC3_NR; i++) {
182 qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
183 writel(0x00000002, &qos_addr->dblgcnt);
184 writel(0x00002096, &qos_addr->dbtmval0);
185 writel(0x00002064, &qos_addr->dbtmval1);
186 writel(0x00002032, &qos_addr->dbtmval2);
187 writel(0x00001FB0, &qos_addr->dbtmval3);
188 writel(0x00000001, &qos_addr->dbrqctr);
189 writel(0x00002078, &qos_addr->dbthres0);
190 writel(0x0000204B, &qos_addr->dbthres1);
191 writel(0x0000201E, &qos_addr->dbthres2);
192 writel(0x00000001, &qos_addr->dblgqon);
193 }
194
195 /* DBSC0 - Write */
196 for (i = DBSC3_00; i < DBSC3_NR; i++) {
197 qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
198 writel(0x00000002, &qos_addr->dblgcnt);
199 writel(0x00002096, &qos_addr->dbtmval0);
200 writel(0x00002064, &qos_addr->dbtmval1);
201 writel(0x00002050, &qos_addr->dbtmval2);
202 writel(0x0000203A, &qos_addr->dbtmval3);
203 writel(0x00000001, &qos_addr->dbrqctr);
204 writel(0x00002078, &qos_addr->dbthres0);
205 writel(0x0000204B, &qos_addr->dbthres1);
206 writel(0x0000203C, &qos_addr->dbthres2);
207 writel(0x00000001, &qos_addr->dblgqon);
208 }
209
210 /* DBSC1 - Read */
211 for (i = DBSC3_00; i < DBSC3_NR; i++) {
212 qos_addr = (struct rcar_dbsc3_qos *)dbsc3_1_r_qos_addr[i];
213 writel(0x00000002, &qos_addr->dblgcnt);
214 writel(0x00002096, &qos_addr->dbtmval0);
215 writel(0x00002064, &qos_addr->dbtmval1);
216 writel(0x00002032, &qos_addr->dbtmval2);
217 writel(0x00001FB0, &qos_addr->dbtmval3);
218 writel(0x00000001, &qos_addr->dbrqctr);
219 writel(0x00002078, &qos_addr->dbthres0);
220 writel(0x0000204B, &qos_addr->dbthres1);
221 writel(0x0000201E, &qos_addr->dbthres2);
222 writel(0x00000001, &qos_addr->dblgqon);
223 }
224
225 /* DBSC1 - Write */
226 for (i = DBSC3_00; i < DBSC3_NR; i++) {
227 qos_addr = (struct rcar_dbsc3_qos *)dbsc3_1_w_qos_addr[i];
228 writel(0x00000002, &qos_addr->dblgcnt);
229 writel(0x00002096, &qos_addr->dbtmval0);
230 writel(0x00002064, &qos_addr->dbtmval1);
231 writel(0x00002050, &qos_addr->dbtmval2);
232 writel(0x0000203A, &qos_addr->dbtmval3);
233 writel(0x00000001, &qos_addr->dbrqctr);
234 writel(0x00002078, &qos_addr->dbthres0);
235 writel(0x0000204B, &qos_addr->dbthres1);
236 writel(0x0000203C, &qos_addr->dbthres2);
237 writel(0x00000001, &qos_addr->dblgqon);
238 }
239
240 /* CCI-400 -QoS */
241 writel(0x20001000, CCI_400_MAXOT_1);
242 writel(0x20001000, CCI_400_MAXOT_2);
243 writel(0x0000000C, CCI_400_QOSCNTL_1);
244 writel(0x0000000C, CCI_400_QOSCNTL_2);
245
246 /* MXI -QoS */
247 /* Transaction Control (MXI) */
248 mxi = (struct rcar_mxi *)MXI_BASE;
249 writel(0x00000013, &mxi->mxrtcr);
250 writel(0x00000013, &mxi->mxwtcr);
251
252 /* QoS Control (MXI) */
253 mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
254 writel(0x0000000C, &mxi_qos->vspdu0);
255 writel(0x0000000C, &mxi_qos->vspdu1);
256 writel(0x0000000E, &mxi_qos->du0);
257 writel(0x0000000D, &mxi_qos->du1);
258
259 /* AXI -QoS */
260 /* Transaction Control (MXI) */
261 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE;
262 writel(0x00000002, &axi_qos->qosconf);
263 writel(0x00002245, &axi_qos->qosctset0);
264 writel(0x00002096, &axi_qos->qosctset1);
265 writel(0x00002030, &axi_qos->qosctset2);
266 writel(0x00002030, &axi_qos->qosctset3);
267 writel(0x00000001, &axi_qos->qosreqctr);
268 writel(0x00002064, &axi_qos->qosthres0);
269 writel(0x00002004, &axi_qos->qosthres1);
270 writel(0x00000000, &axi_qos->qosthres2);
271 writel(0x00000001, &axi_qos->qosqon);
272
273 axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE;
274 writel(0x00000000, &axi_qos->qosconf);
275 writel(0x000020A6, &axi_qos->qosctset0);
276 writel(0x00000001, &axi_qos->qosreqctr);
277 writel(0x00002064, &axi_qos->qosthres0);
278 writel(0x00002004, &axi_qos->qosthres1);
279 writel(0x00000000, &axi_qos->qosthres2);
280 writel(0x00000001, &axi_qos->qosqon);
281
282 axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2D_BASE;
283 writel(0x00000000, &axi_qos->qosconf);
284 writel(0x000020A6, &axi_qos->qosctset0);
285 writel(0x00000001, &axi_qos->qosreqctr);
286 writel(0x00002064, &axi_qos->qosthres0);
287 writel(0x00002004, &axi_qos->qosthres1);
288 writel(0x00000000, &axi_qos->qosthres2);
289 writel(0x00000001, &axi_qos->qosqon);
290
291 axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP0_BASE;
292 writel(0x00000000, &axi_qos->qosconf);
293 writel(0x00002021, &axi_qos->qosctset0);
294 writel(0x00000001, &axi_qos->qosreqctr);
295 writel(0x00002064, &axi_qos->qosthres0);
296 writel(0x00002004, &axi_qos->qosthres1);
297 writel(0x00000000, &axi_qos->qosthres2);
298 writel(0x00000001, &axi_qos->qosqon);
299
300 axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP1_BASE;
301 writel(0x00000000, &axi_qos->qosconf);
302 writel(0x00002037, &axi_qos->qosctset0);
303 writel(0x00000001, &axi_qos->qosreqctr);
304 writel(0x00002064, &axi_qos->qosthres0);
305 writel(0x00002004, &axi_qos->qosthres1);
306 writel(0x00000000, &axi_qos->qosthres2);
307 writel(0x00000001, &axi_qos->qosqon);
308
309 axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE;
310 writel(0x00000002, &axi_qos->qosconf);
311 writel(0x00002245, &axi_qos->qosctset0);
312 writel(0x00002096, &axi_qos->qosctset1);
313 writel(0x00002030, &axi_qos->qosctset2);
314 writel(0x00002030, &axi_qos->qosctset3);
315 writel(0x00000001, &axi_qos->qosreqctr);
316 writel(0x00002064, &axi_qos->qosthres0);
317 writel(0x00002004, &axi_qos->qosthres1);
318 writel(0x00000000, &axi_qos->qosthres2);
319 writel(0x00000001, &axi_qos->qosqon);
320
321 axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE;
322 writel(0x00000002, &axi_qos->qosconf);
323 writel(0x00002245, &axi_qos->qosctset0);
324 writel(0x00002096, &axi_qos->qosctset1);
325 writel(0x00002030, &axi_qos->qosctset2);
326 writel(0x00002030, &axi_qos->qosctset3);
327 writel(0x00000001, &axi_qos->qosreqctr);
328 writel(0x00002064, &axi_qos->qosthres0);
329 writel(0x00002004, &axi_qos->qosthres1);
330 writel(0x00000000, &axi_qos->qosthres2);
331 writel(0x00000001, &axi_qos->qosqon);
332
333 axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE;
334 writel(0x00000002, &axi_qos->qosconf);
335 writel(0x00002245, &axi_qos->qosctset0);
336 writel(0x00002096, &axi_qos->qosctset1);
337 writel(0x00002030, &axi_qos->qosctset2);
338 writel(0x00002030, &axi_qos->qosctset3);
339 writel(0x00000001, &axi_qos->qosreqctr);
340 writel(0x00002064, &axi_qos->qosthres0);
341 writel(0x00002004, &axi_qos->qosthres1);
342 writel(0x00000000, &axi_qos->qosthres2);
343 writel(0x00000001, &axi_qos->qosqon);
344
345 axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE;
346 writel(0x00000000, &axi_qos->qosconf);
347 writel(0x0000214C, &axi_qos->qosctset0);
348 writel(0x00000001, &axi_qos->qosreqctr);
349 writel(0x00002064, &axi_qos->qosthres0);
350 writel(0x00002004, &axi_qos->qosthres1);
351 writel(0x00000000, &axi_qos->qosthres2);
352 writel(0x00000001, &axi_qos->qosqon);
353
354 axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE;
355 writel(0x00000001, &axi_qos->qosconf);
356 writel(0x00002004, &axi_qos->qosctset0);
357 writel(0x00002096, &axi_qos->qosctset1);
358 writel(0x00002030, &axi_qos->qosctset2);
359 writel(0x00002030, &axi_qos->qosctset3);
360 writel(0x00000001, &axi_qos->qosreqctr);
361 writel(0x00002064, &axi_qos->qosthres0);
362 writel(0x00002004, &axi_qos->qosthres1);
363 writel(0x00000000, &axi_qos->qosthres2);
364 writel(0x00000001, &axi_qos->qosqon);
365
366 axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE;
367 writel(0x00000001, &axi_qos->qosconf);
368 writel(0x00002004, &axi_qos->qosctset0);
369 writel(0x00002096, &axi_qos->qosctset1);
370 writel(0x00002030, &axi_qos->qosctset2);
371 writel(0x00002030, &axi_qos->qosctset3);
372 writel(0x00000001, &axi_qos->qosreqctr);
373 writel(0x00002064, &axi_qos->qosthres0);
374 writel(0x00002004, &axi_qos->qosthres1);
375 writel(0x00000000, &axi_qos->qosthres2);
376 writel(0x00000001, &axi_qos->qosqon);
377
378 axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUR_BASE;
379 writel(0x00000001, &axi_qos->qosconf);
380 writel(0x00002004, &axi_qos->qosctset0);
381 writel(0x00002096, &axi_qos->qosctset1);
382 writel(0x00002030, &axi_qos->qosctset2);
383 writel(0x00002030, &axi_qos->qosctset3);
384 writel(0x00000001, &axi_qos->qosreqctr);
385 writel(0x00002064, &axi_qos->qosthres0);
386 writel(0x00002004, &axi_qos->qosthres1);
387 writel(0x00000000, &axi_qos->qosthres2);
388 writel(0x00000001, &axi_qos->qosqon);
389
390 axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE;
391 writel(0x00000001, &axi_qos->qosconf);
392 writel(0x00002004, &axi_qos->qosctset0);
393 writel(0x00002096, &axi_qos->qosctset1);
394 writel(0x00002030, &axi_qos->qosctset2);
395 writel(0x00002030, &axi_qos->qosctset3);
396 writel(0x00000001, &axi_qos->qosreqctr);
397 writel(0x00002064, &axi_qos->qosthres0);
398 writel(0x00002004, &axi_qos->qosthres1);
399 writel(0x00000000, &axi_qos->qosthres2);
400 writel(0x00000001, &axi_qos->qosqon);
401
402 axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE;
403 writel(0x00000001, &axi_qos->qosconf);
404 writel(0x00002004, &axi_qos->qosctset0);
405 writel(0x00002096, &axi_qos->qosctset1);
406 writel(0x00002030, &axi_qos->qosctset2);
407 writel(0x00002030, &axi_qos->qosctset3);
408 writel(0x00000001, &axi_qos->qosreqctr);
409 writel(0x00002064, &axi_qos->qosthres0);
410 writel(0x00002004, &axi_qos->qosthres1);
411 writel(0x00000000, &axi_qos->qosthres2);
412 writel(0x00000001, &axi_qos->qosqon);
413
414 axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB0_BASE;
415 writel(0x00000000, &axi_qos->qosconf);
416 writel(0x00002021, &axi_qos->qosctset0);
417 writel(0x00000001, &axi_qos->qosreqctr);
418 writel(0x00002064, &axi_qos->qosthres0);
419 writel(0x00002004, &axi_qos->qosthres1);
420 writel(0x00000000, &axi_qos->qosthres2);
421 writel(0x00000001, &axi_qos->qosqon);
422
423 axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB1_BASE;
424 writel(0x00000000, &axi_qos->qosconf);
425 writel(0x00002021, &axi_qos->qosctset0);
426 writel(0x00000001, &axi_qos->qosreqctr);
427 writel(0x00002064, &axi_qos->qosthres0);
428 writel(0x00002004, &axi_qos->qosthres1);
429 writel(0x00000000, &axi_qos->qosthres2);
430 writel(0x00000001, &axi_qos->qosqon);
431
432 axi_qos = (struct rcar_axi_qos *)SYS_AXI_PCI_BASE;
433 writel(0x00000000, &axi_qos->qosconf);
434 writel(0x0000214C, &axi_qos->qosctset0);
435 writel(0x00000001, &axi_qos->qosreqctr);
436 writel(0x00002064, &axi_qos->qosthres0);
437 writel(0x00002004, &axi_qos->qosthres1);
438 writel(0x00000000, &axi_qos->qosthres2);
439 writel(0x00000001, &axi_qos->qosqon);
440
441 axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE;
442 writel(0x00000002, &axi_qos->qosconf);
443 writel(0x00002245, &axi_qos->qosctset0);
444 writel(0x00002096, &axi_qos->qosctset1);
445 writel(0x00002030, &axi_qos->qosctset2);
446 writel(0x00002030, &axi_qos->qosctset3);
447 writel(0x00000001, &axi_qos->qosreqctr);
448 writel(0x00002064, &axi_qos->qosthres0);
449 writel(0x00002004, &axi_qos->qosthres1);
450 writel(0x00000000, &axi_qos->qosthres2);
451 writel(0x00000001, &axi_qos->qosqon);
452
453 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE;
454 writel(0x00000000, &axi_qos->qosconf);
455 writel(0x000020A6, &axi_qos->qosctset0);
456 writel(0x00000001, &axi_qos->qosreqctr);
457 writel(0x00002064, &axi_qos->qosthres0);
458 writel(0x00002004, &axi_qos->qosthres1);
459 writel(0x00000000, &axi_qos->qosthres2);
460 writel(0x00000001, &axi_qos->qosqon);
461
462 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE;
463 writel(0x00000000, &axi_qos->qosconf);
464 writel(0x000020A6, &axi_qos->qosctset0);
465 writel(0x00000001, &axi_qos->qosreqctr);
466 writel(0x00002064, &axi_qos->qosthres0);
467 writel(0x00002004, &axi_qos->qosthres1);
468 writel(0x00000000, &axi_qos->qosthres2);
469 writel(0x00000001, &axi_qos->qosqon);
470
471 axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE;
472 writel(0x00000000, &axi_qos->qosconf);
473 writel(0x00002053, &axi_qos->qosctset0);
474 writel(0x00000001, &axi_qos->qosreqctr);
475 writel(0x00002064, &axi_qos->qosthres0);
476 writel(0x00002004, &axi_qos->qosthres1);
477 writel(0x00000000, &axi_qos->qosthres2);
478 writel(0x00000001, &axi_qos->qosqon);
479
480 axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB21_BASE;
481 writel(0x00000000, &axi_qos->qosconf);
482 writel(0x00002053, &axi_qos->qosctset0);
483 writel(0x00000001, &axi_qos->qosreqctr);
484 writel(0x00002064, &axi_qos->qosthres0);
485 writel(0x00002004, &axi_qos->qosthres1);
486 writel(0x00000000, &axi_qos->qosthres2);
487 writel(0x00000001, &axi_qos->qosqon);
488
489 axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE;
490 writel(0x00000000, &axi_qos->qosconf);
491 writel(0x00002053, &axi_qos->qosctset0);
492 writel(0x00000001, &axi_qos->qosreqctr);
493 writel(0x00002064, &axi_qos->qosthres0);
494 writel(0x00002004, &axi_qos->qosthres1);
495 writel(0x00000000, &axi_qos->qosthres2);
496 writel(0x00000001, &axi_qos->qosqon);
497
498 axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB30_BASE;
499 writel(0x00000000, &axi_qos->qosconf);
500 writel(0x0000214C, &axi_qos->qosctset0);
501 writel(0x00000001, &axi_qos->qosreqctr);
502 writel(0x00002064, &axi_qos->qosthres0);
503 writel(0x00002004, &axi_qos->qosthres1);
504 writel(0x00000000, &axi_qos->qosthres2);
505 writel(0x00000001, &axi_qos->qosqon);
506
507 axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE;
508 writel(0x00000002, &axi_qos->qosconf);
509 writel(0x00002245, &axi_qos->qosctset0);
510 writel(0x00000001, &axi_qos->qosreqctr);
511 writel(0x00002064, &axi_qos->qosthres0);
512 writel(0x00002004, &axi_qos->qosthres1);
513 writel(0x00000000, &axi_qos->qosthres2);
514 writel(0x00000001, &axi_qos->qosqon);
515
516 axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE;
517 writel(0x00000000, &axi_qos->qosconf);
518 writel(0x00002029, &axi_qos->qosctset0);
519 writel(0x00000001, &axi_qos->qosreqctr);
520 writel(0x00002064, &axi_qos->qosthres0);
521 writel(0x00002004, &axi_qos->qosthres1);
522 writel(0x00000000, &axi_qos->qosthres2);
523 writel(0x00000001, &axi_qos->qosqon);
524
525 axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE;
526 writel(0x00000002, &axi_qos->qosconf);
527 writel(0x00002245, &axi_qos->qosctset0);
528 writel(0x00000001, &axi_qos->qosreqctr);
529 writel(0x00002064, &axi_qos->qosthres0);
530 writel(0x00002004, &axi_qos->qosthres1);
531 writel(0x00000000, &axi_qos->qosthres2);
532 writel(0x00000001, &axi_qos->qosqon);
533
534 axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE;
535 writel(0x00000000, &axi_qos->qosconf);
536 writel(0x00002053, &axi_qos->qosctset0);
537 writel(0x00000001, &axi_qos->qosreqctr);
538 writel(0x00002064, &axi_qos->qosthres0);
539 writel(0x00002004, &axi_qos->qosthres1);
540 writel(0x00000000, &axi_qos->qosthres2);
541 writel(0x00000001, &axi_qos->qosqon);
542
543 axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE;
544 writel(0x00000000, &axi_qos->qosconf);
545 writel(0x000020A6, &axi_qos->qosctset0);
546 writel(0x00000001, &axi_qos->qosreqctr);
547 writel(0x00002064, &axi_qos->qosthres0);
548 writel(0x00002004, &axi_qos->qosthres1);
549 writel(0x00000000, &axi_qos->qosthres2);
550 writel(0x00000001, &axi_qos->qosqon);
551
552 axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE;
553 writel(0x00000000, &axi_qos->qosconf);
554 writel(0x00002053, &axi_qos->qosctset0);
555 writel(0x00000001, &axi_qos->qosreqctr);
556 writel(0x00002064, &axi_qos->qosthres0);
557 writel(0x00002004, &axi_qos->qosthres1);
558 writel(0x00000000, &axi_qos->qosthres2);
559 writel(0x00000001, &axi_qos->qosqon);
560
561 axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE;
562 writel(0x00000002, &axi_qos->qosconf);
563 writel(0x00002245, &axi_qos->qosctset0);
564 writel(0x00000001, &axi_qos->qosreqctr);
565 writel(0x00002064, &axi_qos->qosthres0);
566 writel(0x00002004, &axi_qos->qosthres1);
567 writel(0x00000000, &axi_qos->qosthres2);
568 writel(0x00000001, &axi_qos->qosqon);
569
570 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT0_BASE;
571 writel(0x00000000, &axi_qos->qosconf);
572 writel(0x00002053, &axi_qos->qosctset0);
573 writel(0x00000001, &axi_qos->qosreqctr);
574 writel(0x00002064, &axi_qos->qosthres0);
575 writel(0x00002004, &axi_qos->qosthres1);
576 writel(0x00000000, &axi_qos->qosthres2);
577 writel(0x00000001, &axi_qos->qosqon);
578
579 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT1_BASE;
580 writel(0x00000000, &axi_qos->qosconf);
581 writel(0x00002053, &axi_qos->qosctset0);
582 writel(0x00000001, &axi_qos->qosreqctr);
583 writel(0x00002064, &axi_qos->qosthres0);
584 writel(0x00002004, &axi_qos->qosthres1);
585 writel(0x00000000, &axi_qos->qosthres2);
586 writel(0x00000001, &axi_qos->qosqon);
587
588 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE;
589 writel(0x00000000, &axi_qos->qosconf);
590 writel(0x0000214C, &axi_qos->qosctset0);
591 writel(0x00000001, &axi_qos->qosreqctr);
592 writel(0x00002064, &axi_qos->qosthres0);
593 writel(0x00002004, &axi_qos->qosthres1);
594 writel(0x00000000, &axi_qos->qosthres2);
595 writel(0x00000001, &axi_qos->qosqon);
596
597 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE;
598 writel(0x00000000, &axi_qos->qosconf);
599 writel(0x0000214C, &axi_qos->qosctset0);
600 writel(0x00000001, &axi_qos->qosreqctr);
601 writel(0x00002064, &axi_qos->qosthres0);
602 writel(0x00002004, &axi_qos->qosthres1);
603 writel(0x00000000, &axi_qos->qosthres2);
604 writel(0x00000001, &axi_qos->qosqon);
605
606 axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE;
607 writel(0x00000000, &axi_qos->qosconf);
608 writel(0x000020A6, &axi_qos->qosctset0);
609 writel(0x00000001, &axi_qos->qosreqctr);
610 writel(0x00002064, &axi_qos->qosthres0);
611 writel(0x00002004, &axi_qos->qosthres1);
612 writel(0x00000000, &axi_qos->qosthres2);
613 writel(0x00000001, &axi_qos->qosqon);
614
615 axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE;
616 writel(0x00000000, &axi_qos->qosconf);
617 writel(0x00002053, &axi_qos->qosctset0);
618 writel(0x00000001, &axi_qos->qosreqctr);
619 writel(0x00002064, &axi_qos->qosthres0);
620 writel(0x00002004, &axi_qos->qosthres1);
621 writel(0x00000000, &axi_qos->qosthres2);
622 writel(0x00000001, &axi_qos->qosqon);
623
624 axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE;
625 writel(0x00000000, &axi_qos->qosconf);
626 writel(0x00002053, &axi_qos->qosctset0);
627 writel(0x00000001, &axi_qos->qosreqctr);
628 writel(0x00002064, &axi_qos->qosthres0);
629 writel(0x00002004, &axi_qos->qosthres1);
630 writel(0x00000000, &axi_qos->qosthres2);
631 writel(0x00000001, &axi_qos->qosqon);
632
633 /* QoS Register (RT-AXI) */
634 axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
635 writel(0x00000000, &axi_qos->qosconf);
636 writel(0x00002053, &axi_qos->qosctset0);
637 writel(0x00002096, &axi_qos->qosctset1);
638 writel(0x00002030, &axi_qos->qosctset2);
639 writel(0x00002030, &axi_qos->qosctset3);
640 writel(0x00000001, &axi_qos->qosreqctr);
641 writel(0x00002064, &axi_qos->qosthres0);
642 writel(0x00002004, &axi_qos->qosthres1);
643 writel(0x00000000, &axi_qos->qosthres2);
644 writel(0x00000001, &axi_qos->qosqon);
645
646 axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE;
647 writel(0x00000000, &axi_qos->qosconf);
648 writel(0x00002053, &axi_qos->qosctset0);
649 writel(0x00002096, &axi_qos->qosctset1);
650 writel(0x00002030, &axi_qos->qosctset2);
651 writel(0x00002030, &axi_qos->qosctset3);
652 writel(0x00000001, &axi_qos->qosreqctr);
653 writel(0x00002064, &axi_qos->qosthres0);
654 writel(0x00002004, &axi_qos->qosthres1);
655 writel(0x00000000, &axi_qos->qosthres2);
656 writel(0x00000001, &axi_qos->qosqon);
657
658 axi_qos = (struct rcar_axi_qos *)RT_AXI_RDM_BASE;
659 writel(0x00000000, &axi_qos->qosconf);
660 writel(0x00002299, &axi_qos->qosctset0);
661 writel(0x00000001, &axi_qos->qosreqctr);
662 writel(0x00002064, &axi_qos->qosthres0);
663 writel(0x00002004, &axi_qos->qosthres1);
664 writel(0x00000000, &axi_qos->qosthres2);
665 writel(0x00000001, &axi_qos->qosqon);
666
667 axi_qos = (struct rcar_axi_qos *)RT_AXI_RDS_BASE;
668 writel(0x00000000, &axi_qos->qosconf);
669 writel(0x00002029, &axi_qos->qosctset0);
670 writel(0x00000001, &axi_qos->qosreqctr);
671 writel(0x00002064, &axi_qos->qosthres0);
672 writel(0x00002004, &axi_qos->qosthres1);
673 writel(0x00000000, &axi_qos->qosthres2);
674 writel(0x00000001, &axi_qos->qosqon);
675
676 axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE;
677 writel(0x00000002, &axi_qos->qosconf);
678 writel(0x00002245, &axi_qos->qosctset0);
679 writel(0x00002096, &axi_qos->qosctset1);
680 writel(0x00002030, &axi_qos->qosctset2);
681 writel(0x00002030, &axi_qos->qosctset3);
682 writel(0x00000001, &axi_qos->qosreqctr);
683 writel(0x00002064, &axi_qos->qosthres0);
684 writel(0x00002004, &axi_qos->qosthres1);
685 writel(0x00000000, &axi_qos->qosthres2);
686 writel(0x00000001, &axi_qos->qosqon);
687
688 axi_qos = (struct rcar_axi_qos *)RT_AXI_STPRO_BASE;
689 writel(0x00000000, &axi_qos->qosconf);
690 writel(0x00002029, &axi_qos->qosctset0);
691 writel(0x00002096, &axi_qos->qosctset1);
692 writel(0x00002030, &axi_qos->qosctset2);
693 writel(0x00002030, &axi_qos->qosctset3);
694 writel(0x00000001, &axi_qos->qosreqctr);
695 writel(0x00002064, &axi_qos->qosthres0);
696 writel(0x00002004, &axi_qos->qosthres1);
697 writel(0x00000000, &axi_qos->qosthres2);
698 writel(0x00000001, &axi_qos->qosqon);
699
700 axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE;
701 writel(0x00000002, &axi_qos->qosconf);
702 writel(0x00002245, &axi_qos->qosctset0);
703 writel(0x00000001, &axi_qos->qosreqctr);
704 writel(0x00002064, &axi_qos->qosthres0);
705 writel(0x00002004, &axi_qos->qosthres1);
706 writel(0x00000000, &axi_qos->qosthres2);
707 writel(0x00000001, &axi_qos->qosqon);
708
709 /* QoS Register (MP-AXI) */
710 axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE;
711 writel(0x00000000, &axi_qos->qosconf);
712 writel(0x00002037, &axi_qos->qosctset0);
713 writel(0x00000001, &axi_qos->qosreqctr);
714 writel(0x00002064, &axi_qos->qosthres0);
715 writel(0x00002004, &axi_qos->qosthres1);
716 writel(0x00000000, &axi_qos->qosthres2);
717 writel(0x00000001, &axi_qos->qosqon);
718
719 axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE;
720 writel(0x00000001, &axi_qos->qosconf);
721 writel(0x00002014, &axi_qos->qosctset0);
722 writel(0x00000040, &axi_qos->qosreqctr);
723 writel(0x00002064, &axi_qos->qosthres0);
724 writel(0x00002004, &axi_qos->qosthres1);
725 writel(0x00000000, &axi_qos->qosthres2);
726 writel(0x00000001, &axi_qos->qosqon);
727
728 axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE;
729 writel(0x00000001, &axi_qos->qosconf);
730 writel(0x00002014, &axi_qos->qosctset0);
731 writel(0x00000040, &axi_qos->qosreqctr);
732 writel(0x00002064, &axi_qos->qosthres0);
733 writel(0x00002004, &axi_qos->qosthres1);
734 writel(0x00000000, &axi_qos->qosthres2);
735 writel(0x00000001, &axi_qos->qosqon);
736
737 axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE;
738 writel(0x00000001, &axi_qos->qosconf);
739 writel(0x00001FF0, &axi_qos->qosctset0);
740 writel(0x00000020, &axi_qos->qosreqctr);
741 writel(0x00002064, &axi_qos->qosthres0);
742 writel(0x00002004, &axi_qos->qosthres1);
743 writel(0x00002001, &axi_qos->qosthres2);
744 writel(0x00000001, &axi_qos->qosqon);
745
746 axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE;
747 writel(0x00000001, &axi_qos->qosconf);
748 writel(0x00002004, &axi_qos->qosctset0);
749 writel(0x00002096, &axi_qos->qosctset1);
750 writel(0x00002030, &axi_qos->qosctset2);
751 writel(0x00002030, &axi_qos->qosctset3);
752 writel(0x00000001, &axi_qos->qosreqctr);
753 writel(0x00002064, &axi_qos->qosthres0);
754 writel(0x00002004, &axi_qos->qosthres1);
755 writel(0x00000000, &axi_qos->qosthres2);
756 writel(0x00000001, &axi_qos->qosqon);
757
758 axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE;
759 writel(0x00000000, &axi_qos->qosconf);
760 writel(0x00002053, &axi_qos->qosctset0);
761 writel(0x00000001, &axi_qos->qosreqctr);
762 writel(0x00002064, &axi_qos->qosthres0);
763 writel(0x00002004, &axi_qos->qosthres1);
764 writel(0x00000000, &axi_qos->qosthres2);
765 writel(0x00000001, &axi_qos->qosqon);
766
767 axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE;
768 writel(0x00000000, &axi_qos->qosconf);
769 writel(0x0000206E, &axi_qos->qosctset0);
770 writel(0x00000001, &axi_qos->qosreqctr);
771 writel(0x00002064, &axi_qos->qosthres0);
772 writel(0x00002004, &axi_qos->qosthres1);
773 writel(0x00000000, &axi_qos->qosthres2);
774 writel(0x00000001, &axi_qos->qosqon);
775
776 /* QoS Register (SYS-AXI256) */
777 axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
778 writel(0x00000002, &axi_qos->qosconf);
779 if (IS_R8A7791_ES2())
780 writel(0x000020EB, &axi_qos->qosctset0);
781 else
782 writel(0x00002245, &axi_qos->qosctset0);
783 writel(0x00002096, &axi_qos->qosctset1);
784 writel(0x00002030, &axi_qos->qosctset2);
785 writel(0x00002030, &axi_qos->qosctset3);
786 writel(0x00000001, &axi_qos->qosreqctr);
787 writel(0x00002064, &axi_qos->qosthres0);
788 writel(0x00002004, &axi_qos->qosthres1);
789 writel(0x00000000, &axi_qos->qosthres2);
790 writel(0x00000001, &axi_qos->qosqon);
791
792 axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE;
793 writel(0x00000002, &axi_qos->qosconf);
794 if (IS_R8A7791_ES2())
795 writel(0x000020EB, &axi_qos->qosctset0);
796 else
797 writel(0x00002245, &axi_qos->qosctset0);
798 writel(0x00002096, &axi_qos->qosctset1);
799 writel(0x00002030, &axi_qos->qosctset2);
800 writel(0x00002030, &axi_qos->qosctset3);
801 writel(0x00000001, &axi_qos->qosreqctr);
802 writel(0x00002064, &axi_qos->qosthres0);
803 writel(0x00002004, &axi_qos->qosthres1);
804 writel(0x00000000, &axi_qos->qosthres2);
805 writel(0x00000001, &axi_qos->qosqon);
806
807 axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE;
808 writel(0x00000002, &axi_qos->qosconf);
809 if (IS_R8A7791_ES2())
810 writel(0x000020EB, &axi_qos->qosctset0);
811 else
812 writel(0x00002245, &axi_qos->qosctset0);
813 writel(0x00002096, &axi_qos->qosctset1);
814 writel(0x00002030, &axi_qos->qosctset2);
815 writel(0x00002030, &axi_qos->qosctset3);
816 writel(0x00000001, &axi_qos->qosreqctr);
817 writel(0x00002064, &axi_qos->qosthres0);
818 writel(0x00002004, &axi_qos->qosthres1);
819 writel(0x00000000, &axi_qos->qosthres2);
820 writel(0x00000001, &axi_qos->qosqon);
821
822 axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE;
823 writel(0x00000002, &axi_qos->qosconf);
824 writel(0x00002245, &axi_qos->qosctset0);
825 writel(0x00002096, &axi_qos->qosctset1);
826 writel(0x00002030, &axi_qos->qosctset2);
827 writel(0x00002030, &axi_qos->qosctset3);
828 writel(0x00000001, &axi_qos->qosreqctr);
829 writel(0x00002064, &axi_qos->qosthres0);
830 writel(0x00002004, &axi_qos->qosthres1);
831 writel(0x00000000, &axi_qos->qosthres2);
832 writel(0x00000001, &axi_qos->qosqon);
833
834 /* QoS Register (CCI-AXI) */
835 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE;
836 writel(0x00000001, &axi_qos->qosconf);
837 writel(0x00002004, &axi_qos->qosctset0);
838 writel(0x00002096, &axi_qos->qosctset1);
839 writel(0x00002030, &axi_qos->qosctset2);
840 writel(0x00002030, &axi_qos->qosctset3);
841 writel(0x00000001, &axi_qos->qosreqctr);
842 writel(0x00002064, &axi_qos->qosthres0);
843 writel(0x00002004, &axi_qos->qosthres1);
844 writel(0x00000000, &axi_qos->qosthres2);
845 writel(0x00000001, &axi_qos->qosqon);
846
847 axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE;
848 writel(0x00000002, &axi_qos->qosconf);
849 writel(0x00002245, &axi_qos->qosctset0);
850 writel(0x00002096, &axi_qos->qosctset1);
851 writel(0x00002030, &axi_qos->qosctset2);
852 writel(0x00002030, &axi_qos->qosctset3);
853 writel(0x00000001, &axi_qos->qosreqctr);
854 writel(0x00002064, &axi_qos->qosthres0);
855 writel(0x00002004, &axi_qos->qosthres1);
856 writel(0x00000000, &axi_qos->qosthres2);
857 writel(0x00000001, &axi_qos->qosqon);
858
859 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE;
860 writel(0x00000001, &axi_qos->qosconf);
861 writel(0x00002004, &axi_qos->qosctset0);
862 writel(0x00002096, &axi_qos->qosctset1);
863 writel(0x00002030, &axi_qos->qosctset2);
864 writel(0x00002030, &axi_qos->qosctset3);
865 writel(0x00000001, &axi_qos->qosreqctr);
866 writel(0x00002064, &axi_qos->qosthres0);
867 writel(0x00002004, &axi_qos->qosthres1);
868 writel(0x00000000, &axi_qos->qosthres2);
869 writel(0x00000001, &axi_qos->qosqon);
870
871 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE;
872 writel(0x00000001, &axi_qos->qosconf);
873 writel(0x00002004, &axi_qos->qosctset0);
874 writel(0x00002096, &axi_qos->qosctset1);
875 writel(0x00002030, &axi_qos->qosctset2);
876 writel(0x00002030, &axi_qos->qosctset3);
877 writel(0x00000001, &axi_qos->qosreqctr);
878 writel(0x00002064, &axi_qos->qosthres0);
879 writel(0x00002004, &axi_qos->qosthres1);
880 writel(0x00000000, &axi_qos->qosthres2);
881 writel(0x00000001, &axi_qos->qosqon);
882
883 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE;
884 writel(0x00000001, &axi_qos->qosconf);
885 writel(0x00002004, &axi_qos->qosctset0);
886 writel(0x00002096, &axi_qos->qosctset1);
887 writel(0x00002030, &axi_qos->qosctset2);
888 writel(0x00002030, &axi_qos->qosctset3);
889 writel(0x00000001, &axi_qos->qosreqctr);
890 writel(0x00002064, &axi_qos->qosthres0);
891 writel(0x00002004, &axi_qos->qosthres1);
892 writel(0x00000000, &axi_qos->qosthres2);
893 writel(0x00000001, &axi_qos->qosqon);
894
895 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE;
896 writel(0x00000002, &axi_qos->qosconf);
897 writel(0x00002245, &axi_qos->qosctset0);
898 writel(0x00002096, &axi_qos->qosctset1);
899 writel(0x00002030, &axi_qos->qosctset2);
900 writel(0x00002030, &axi_qos->qosctset3);
901 writel(0x00000001, &axi_qos->qosreqctr);
902 writel(0x00002064, &axi_qos->qosthres0);
903 writel(0x00002004, &axi_qos->qosthres1);
904 writel(0x00000000, &axi_qos->qosthres2);
905 writel(0x00000001, &axi_qos->qosqon);
906
907 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE;
908 writel(0x00000001, &axi_qos->qosconf);
909 writel(0x00002004, &axi_qos->qosctset0);
910 writel(0x00002096, &axi_qos->qosctset1);
911 writel(0x00002030, &axi_qos->qosctset2);
912 writel(0x00002030, &axi_qos->qosctset3);
913 writel(0x00000001, &axi_qos->qosreqctr);
914 writel(0x00002064, &axi_qos->qosthres0);
915 writel(0x00002004, &axi_qos->qosthres1);
916 writel(0x00000000, &axi_qos->qosthres2);
917 writel(0x00000001, &axi_qos->qosqon);
918
919 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE;
920 writel(0x00000001, &axi_qos->qosconf);
921 writel(0x00002004, &axi_qos->qosctset0);
922 writel(0x00002096, &axi_qos->qosctset1);
923 writel(0x00002030, &axi_qos->qosctset2);
924 writel(0x00002030, &axi_qos->qosctset3);
925 writel(0x00000001, &axi_qos->qosreqctr);
926 writel(0x00002064, &axi_qos->qosthres0);
927 writel(0x00002004, &axi_qos->qosthres1);
928 writel(0x00000000, &axi_qos->qosthres2);
929 writel(0x00000001, &axi_qos->qosqon);
930
931 /* QoS Register (Media-AXI) */
932 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE;
933 writel(0x00000002, &axi_qos->qosconf);
934 writel(0x000020DC, &axi_qos->qosctset0);
935 writel(0x00002096, &axi_qos->qosctset1);
936 writel(0x00002030, &axi_qos->qosctset2);
937 writel(0x00002030, &axi_qos->qosctset3);
938 writel(0x00000020, &axi_qos->qosreqctr);
939 writel(0x000020AA, &axi_qos->qosthres0);
940 writel(0x00002032, &axi_qos->qosthres1);
941 writel(0x00000001, &axi_qos->qosthres2);
942
943 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE;
944 writel(0x00000002, &axi_qos->qosconf);
945 writel(0x000020DC, &axi_qos->qosctset0);
946 writel(0x00002096, &axi_qos->qosctset1);
947 writel(0x00002030, &axi_qos->qosctset2);
948 writel(0x00002030, &axi_qos->qosctset3);
949 writel(0x00000020, &axi_qos->qosreqctr);
950 writel(0x000020AA, &axi_qos->qosthres0);
951 writel(0x00002032, &axi_qos->qosthres1);
952 writel(0x00000001, &axi_qos->qosthres2);
953
954 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPR_BASE;
955 writel(0x00000001, &axi_qos->qosconf);
956 writel(0x00002190, &axi_qos->qosctset0);
957 writel(0x00000020, &axi_qos->qosreqctr);
958 writel(0x00002064, &axi_qos->qosthres0);
959 writel(0x00002004, &axi_qos->qosthres1);
960 writel(0x00000001, &axi_qos->qosthres2);
961 writel(0x00000001, &axi_qos->qosqon);
962
963 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPW_BASE;
964 writel(0x00000001, &axi_qos->qosconf);
965 writel(0x00002190, &axi_qos->qosctset0);
966 writel(0x00000020, &axi_qos->qosreqctr);
967 if (IS_R8A7791_ES2()) {
968 writel(0x00000001, &axi_qos->qosthres0);
969 writel(0x00000001, &axi_qos->qosthres1);
970 } else {
971 writel(0x00002064, &axi_qos->qosthres0);
972 writel(0x00002004, &axi_qos->qosthres1);
973 }
974 writel(0x00000001, &axi_qos->qosthres2);
975 writel(0x00000001, &axi_qos->qosqon);
976
977 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE;
978 writel(0x00000001, &axi_qos->qosconf);
979 writel(0x00002190, &axi_qos->qosctset0);
980 writel(0x00000020, &axi_qos->qosreqctr);
981 writel(0x00002064, &axi_qos->qosthres0);
982 writel(0x00002004, &axi_qos->qosthres1);
983 writel(0x00000001, &axi_qos->qosthres2);
984 writel(0x00000001, &axi_qos->qosqon);
985
986 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE;
987 writel(0x00000001, &axi_qos->qosconf);
988 writel(0x00002190, &axi_qos->qosctset0);
989 writel(0x00000020, &axi_qos->qosreqctr);
990 writel(0x00002064, &axi_qos->qosthres0);
991 writel(0x00002004, &axi_qos->qosthres1);
992 writel(0x00000001, &axi_qos->qosthres2);
993 writel(0x00000001, &axi_qos->qosqon);
994
995 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
996 writel(0x00000001, &axi_qos->qosconf);
997 writel(0x00002190, &axi_qos->qosctset0);
998 writel(0x00000020, &axi_qos->qosreqctr);
999 writel(0x00002064, &axi_qos->qosthres0);
1000 writel(0x00002004, &axi_qos->qosthres1);
1001 writel(0x00000001, &axi_qos->qosthres2);
1002 writel(0x00000001, &axi_qos->qosqon);
1003
1004 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
1005 writel(0x00000001, &axi_qos->qosconf);
1006 writel(0x00002190, &axi_qos->qosctset0);
1007 writel(0x00000020, &axi_qos->qosreqctr);
1008 if (IS_R8A7791_ES2()) {
1009 writel(0x00000001, &axi_qos->qosthres0);
1010 writel(0x00000001, &axi_qos->qosthres1);
1011 } else {
1012 writel(0x00002064, &axi_qos->qosthres0);
1013 writel(0x00002004, &axi_qos->qosthres1);
1014 }
1015 writel(0x00000001, &axi_qos->qosthres2);
1016 writel(0x00000001, &axi_qos->qosqon);
1017
1018 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
1019 writel(0x00000001, &axi_qos->qosconf);
1020 writel(0x00002190, &axi_qos->qosctset0);
1021 writel(0x00000020, &axi_qos->qosreqctr);
1022 writel(0x00002064, &axi_qos->qosthres0);
1023 writel(0x00002004, &axi_qos->qosthres1);
1024 writel(0x00000001, &axi_qos->qosthres2);
1025 writel(0x00000001, &axi_qos->qosqon);
1026
1027 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
1028 writel(0x00000001, &axi_qos->qosconf);
1029 writel(0x00002190, &axi_qos->qosctset0);
1030 writel(0x00000020, &axi_qos->qosreqctr);
1031 if (IS_R8A7791_ES2()) {
1032 writel(0x00000001, &axi_qos->qosthres0);
1033 writel(0x00000001, &axi_qos->qosthres1);
1034 } else {
1035 writel(0x00002064, &axi_qos->qosthres0);
1036 writel(0x00002004, &axi_qos->qosthres1);
1037 }
1038 writel(0x00000001, &axi_qos->qosthres2);
1039 writel(0x00000001, &axi_qos->qosqon);
1040
1041 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE;
1042 writel(0x00000001, &axi_qos->qosconf);
1043 writel(0x00002190, &axi_qos->qosctset0);
1044 writel(0x00000020, &axi_qos->qosreqctr);
1045 writel(0x00002064, &axi_qos->qosthres0);
1046 writel(0x00002004, &axi_qos->qosthres1);
1047 writel(0x00000001, &axi_qos->qosthres2);
1048 writel(0x00000001, &axi_qos->qosqon);
1049
1050 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE;
1051 writel(0x00000001, &axi_qos->qosconf);
1052 writel(0x00002190, &axi_qos->qosctset0);
1053 writel(0x00000020, &axi_qos->qosreqctr);
1054 if (IS_R8A7791_ES2()) {
1055 writel(0x00000001, &axi_qos->qosthres0);
1056 writel(0x00000001, &axi_qos->qosthres1);
1057 } else {
1058 writel(0x00002064, &axi_qos->qosthres0);
1059 writel(0x00002004, &axi_qos->qosthres1);
1060 }
1061 writel(0x00000001, &axi_qos->qosthres2);
1062 writel(0x00000001, &axi_qos->qosqon);
1063
1064 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE;
1065 writel(0x00000001, &axi_qos->qosconf);
1066 if (IS_R8A7791_ES2())
1067 writel(0x00001FF0, &axi_qos->qosctset0);
1068 else
1069 writel(0x000020C8, &axi_qos->qosctset0);
1070 writel(0x00000020, &axi_qos->qosreqctr);
1071 writel(0x00002064, &axi_qos->qosthres0);
1072 writel(0x00002004, &axi_qos->qosthres1);
1073 if (IS_R8A7791_ES2())
1074 writel(0x00002001, &axi_qos->qosthres2);
1075 else
1076 writel(0x00000001, &axi_qos->qosthres2);
1077 writel(0x00000001, &axi_qos->qosqon);
1078
1079 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE;
1080 writel(0x00000001, &axi_qos->qosconf);
1081 writel(0x000020C8, &axi_qos->qosctset0);
1082 writel(0x00000020, &axi_qos->qosreqctr);
1083 writel(0x00002064, &axi_qos->qosthres0);
1084 writel(0x00002004, &axi_qos->qosthres1);
1085 writel(0x00000001, &axi_qos->qosthres2);
1086 writel(0x00000001, &axi_qos->qosqon);
1087
1088 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE;
1089 writel(0x00000001, &axi_qos->qosconf);
1090 writel(0x000020C8, &axi_qos->qosctset0);
1091 writel(0x00000020, &axi_qos->qosreqctr);
1092 if (IS_R8A7791_ES2()) {
1093 writel(0x00000001, &axi_qos->qosthres0);
1094 writel(0x00000001, &axi_qos->qosthres1);
1095 } else {
1096 writel(0x00002064, &axi_qos->qosthres0);
1097 writel(0x00002004, &axi_qos->qosthres1);
1098 }
1099 writel(0x00000001, &axi_qos->qosthres2);
1100 writel(0x00000001, &axi_qos->qosqon);
1101
1102 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE;
1103 writel(0x00000001, &axi_qos->qosconf);
1104 writel(0x000020C8, &axi_qos->qosctset0);
1105 writel(0x00000020, &axi_qos->qosreqctr);
1106 writel(0x00002064, &axi_qos->qosthres0);
1107 writel(0x00002004, &axi_qos->qosthres1);
1108 writel(0x00000001, &axi_qos->qosthres2);
1109 writel(0x00000001, &axi_qos->qosqon);
1110
1111 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE;
1112 writel(0x00000001, &axi_qos->qosconf);
1113 writel(0x000020C8, &axi_qos->qosctset0);
1114 writel(0x00000020, &axi_qos->qosreqctr);
1115 writel(0x00002064, &axi_qos->qosthres0);
1116 writel(0x00002004, &axi_qos->qosthres1);
1117 writel(0x00000001, &axi_qos->qosthres2);
1118 writel(0x00000001, &axi_qos->qosqon);
1119
1120 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE;
1121 writel(0x00000001, &axi_qos->qosconf);
1122 writel(0x000020C8, &axi_qos->qosctset0);
1123 writel(0x00000020, &axi_qos->qosreqctr);
1124 writel(0x00002064, &axi_qos->qosthres0);
1125 writel(0x00002004, &axi_qos->qosthres1);
1126 writel(0x00000001, &axi_qos->qosthres2);
1127 writel(0x00000001, &axi_qos->qosqon);
1128
1129 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE;
1130 writel(0x00000001, &axi_qos->qosconf);
1131 writel(0x000020C8, &axi_qos->qosctset0);
1132 writel(0x00000020, &axi_qos->qosreqctr);
1133 if (IS_R8A7791_ES2()) {
1134 writel(0x00000001, &axi_qos->qosthres0);
1135 writel(0x00000001, &axi_qos->qosthres1);
1136 } else {
1137 writel(0x00002064, &axi_qos->qosthres0);
1138 writel(0x00002004, &axi_qos->qosthres1);
1139 }
1140 writel(0x00000001, &axi_qos->qosthres2);
1141 writel(0x00000001, &axi_qos->qosqon);
1142
1143 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1R_BASE;
1144 writel(0x00000001, &axi_qos->qosconf);
1145 writel(0x000020C8, &axi_qos->qosctset0);
1146 writel(0x00000020, &axi_qos->qosreqctr);
1147 writel(0x00002064, &axi_qos->qosthres0);
1148 writel(0x00002004, &axi_qos->qosthres1);
1149 writel(0x00000001, &axi_qos->qosthres2);
1150 writel(0x00000001, &axi_qos->qosqon);
1151
1152 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1W_BASE;
1153 writel(0x00000001, &axi_qos->qosconf);
1154 writel(0x000020C8, &axi_qos->qosctset0);
1155 writel(0x00000020, &axi_qos->qosreqctr);
1156 if (IS_R8A7791_ES2()) {
1157 writel(0x00000001, &axi_qos->qosthres0);
1158 writel(0x00000001, &axi_qos->qosthres1);
1159 } else {
1160 writel(0x00002064, &axi_qos->qosthres0);
1161 writel(0x00002004, &axi_qos->qosthres1);
1162 }
1163 writel(0x00000001, &axi_qos->qosthres2);
1164 writel(0x00000001, &axi_qos->qosqon);
1165
1166 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE;
1167 writel(0x00000001, &axi_qos->qosconf);
1168 writel(0x000020C8, &axi_qos->qosctset0);
1169 writel(0x00000020, &axi_qos->qosreqctr);
1170 writel(0x00002064, &axi_qos->qosthres0);
1171 writel(0x00002004, &axi_qos->qosthres1);
1172 writel(0x00000001, &axi_qos->qosthres2);
1173 writel(0x00000001, &axi_qos->qosqon);
1174
1175 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE;
1176 writel(0x00000001, &axi_qos->qosconf);
1177 writel(0x000020C8, &axi_qos->qosctset0);
1178 writel(0x00000020, &axi_qos->qosreqctr);
1179 writel(0x00002064, &axi_qos->qosthres0);
1180 writel(0x00002004, &axi_qos->qosthres1);
1181 writel(0x00000001, &axi_qos->qosthres2);
1182 writel(0x00000001, &axi_qos->qosqon);
1183
1184 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
1185 if (IS_R8A7791_ES2())
1186 writel(0x00000003, &axi_qos->qosconf);
1187 else
1188 writel(0x00000000, &axi_qos->qosconf);
1189 writel(0x000020C8, &axi_qos->qosctset0);
1190 writel(0x00002064, &axi_qos->qosthres0);
1191 writel(0x00002004, &axi_qos->qosthres1);
1192 writel(0x00000001, &axi_qos->qosthres2);
1193 writel(0x00000001, &axi_qos->qosqon);
1194
1195 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
1196 if (IS_R8A7791_ES2())
1197 writel(0x00000003, &axi_qos->qosconf);
1198 else
1199 writel(0x00000000, &axi_qos->qosconf);
1200 writel(0x000020C8, &axi_qos->qosctset0);
1201 writel(0x00002064, &axi_qos->qosthres0);
1202 writel(0x00002004, &axi_qos->qosthres1);
1203 writel(0x00000001, &axi_qos->qosthres2);
1204 writel(0x00000001, &axi_qos->qosqon);
1205
1206 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1R_BASE;
1207 if (IS_R8A7791_ES2())
1208 writel(0x00000003, &axi_qos->qosconf);
1209 else
1210 writel(0x00000000, &axi_qos->qosconf);
1211 writel(0x000020C8, &axi_qos->qosctset0);
1212 writel(0x00002064, &axi_qos->qosthres0);
1213 writel(0x00002004, &axi_qos->qosthres1);
1214 writel(0x00000001, &axi_qos->qosthres2);
1215 writel(0x00000001, &axi_qos->qosqon);
1216
1217 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1W_BASE;
1218 if (IS_R8A7791_ES2())
1219 writel(0x00000003, &axi_qos->qosconf);
1220 else
1221 writel(0x00000000, &axi_qos->qosconf);
1222 writel(0x000020C8, &axi_qos->qosctset0);
1223 writel(0x00002064, &axi_qos->qosthres0);
1224 writel(0x00002004, &axi_qos->qosthres1);
1225 writel(0x00000001, &axi_qos->qosthres2);
1226 writel(0x00000001, &axi_qos->qosqon);
1227
1228 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE;
1229 if (IS_R8A7791_ES2())
1230 writel(0x00000003, &axi_qos->qosconf);
1231 else
1232 writel(0x00000000, &axi_qos->qosconf);
1233 writel(0x00002063, &axi_qos->qosctset0);
1234 writel(0x00000001, &axi_qos->qosreqctr);
1235 writel(0x00002064, &axi_qos->qosthres0);
1236 writel(0x00002004, &axi_qos->qosthres1);
1237 writel(0x00000001, &axi_qos->qosthres2);
1238 writel(0x00000001, &axi_qos->qosqon);
1239
1240 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE;
1241 if (IS_R8A7791_ES2())
1242 writel(0x00000000, &axi_qos->qosconf);
1243 else
1244 writel(0x00000000, &axi_qos->qosconf);
1245 writel(0x00002063, &axi_qos->qosctset0);
1246 writel(0x00000001, &axi_qos->qosreqctr);
1247 writel(0x00002064, &axi_qos->qosthres0);
1248 writel(0x00002004, &axi_qos->qosthres1);
1249 writel(0x00000001, &axi_qos->qosthres2);
1250 writel(0x00000001, &axi_qos->qosqon);
1251
1252 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
1253 writel(0x00000001, &axi_qos->qosconf);
1254 writel(0x00002073, &axi_qos->qosctset0);
1255 writel(0x00000020, &axi_qos->qosreqctr);
1256 writel(0x00002064, &axi_qos->qosthres0);
1257 writel(0x00002004, &axi_qos->qosthres1);
1258 writel(0x00000001, &axi_qos->qosthres2);
1259 writel(0x00000001, &axi_qos->qosqon);
1260
1261 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
1262 writel(0x00000001, &axi_qos->qosconf);
1263 writel(0x00002073, &axi_qos->qosctset0);
1264 writel(0x00000020, &axi_qos->qosreqctr);
1265 if (IS_R8A7791_ES2()) {
1266 writel(0x00000001, &axi_qos->qosthres0);
1267 writel(0x00000001, &axi_qos->qosthres1);
1268 } else {
1269 writel(0x00002064, &axi_qos->qosthres0);
1270 writel(0x00002004, &axi_qos->qosthres1);
1271 }
1272 writel(0x00000001, &axi_qos->qosthres2);
1273 writel(0x00000001, &axi_qos->qosqon);
1274
1275 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
1276 writel(0x00000001, &axi_qos->qosconf);
1277 writel(0x00002073, &axi_qos->qosctset0);
1278 writel(0x00000020, &axi_qos->qosreqctr);
1279 writel(0x00002064, &axi_qos->qosthres0);
1280 writel(0x00002004, &axi_qos->qosthres1);
1281 writel(0x00000001, &axi_qos->qosthres2);
1282 writel(0x00000001, &axi_qos->qosqon);
1283
1284 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
1285 writel(0x00000001, &axi_qos->qosconf);
1286 writel(0x00002073, &axi_qos->qosctset0);
1287 writel(0x00000020, &axi_qos->qosreqctr);
1288 if (IS_R8A7791_ES2()) {
1289 writel(0x00000001, &axi_qos->qosthres0);
1290 writel(0x00000001, &axi_qos->qosthres1);
1291 } else {
1292 writel(0x00002064, &axi_qos->qosthres0);
1293 writel(0x00002004, &axi_qos->qosthres1);
1294 }
1295 writel(0x00000001, &axi_qos->qosthres2);
1296 writel(0x00000001, &axi_qos->qosqon);
1297
1298 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE;
1299 writel(0x00000001, &axi_qos->qosconf);
1300 writel(0x00002073, &axi_qos->qosctset0);
1301 writel(0x00000020, &axi_qos->qosreqctr);
1302 writel(0x00002064, &axi_qos->qosthres0);
1303 writel(0x00002004, &axi_qos->qosthres1);
1304 writel(0x00000001, &axi_qos->qosthres2);
1305 writel(0x00000001, &axi_qos->qosqon);
1306}
Nobuhiro Iwamatsu7c112732015-10-10 05:58:28 +0900[diff] [blame]1307#else /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
Vladimir Barinov2f8c00e2015-02-14 01:06:13 +0300[diff] [blame]1308void qos_init(void)
1309{
1310}
Nobuhiro Iwamatsu7c112732015-10-10 05:58:28 +0900[diff] [blame]1311#endif /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */