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Heiko Schocherac1956e2006-04-20 08:42:42 +02001/*
Jens Scharsig2686eff2012-05-02 00:57:08 +00002 * Configuation settings for the BuS EB+CPU5283 boards (aka EB+MCF-EV123)
Heiko Schocherac1956e2006-04-20 08:42:42 +02003 *
Jens Scharsig772d9b02009-07-24 10:31:48 +02004 * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
Heiko Schocherac1956e2006-04-20 08:42:42 +02005 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Heiko Schocherac1956e2006-04-20 08:42:42 +02007 */
8
Jens Scharsig2686eff2012-05-02 00:57:08 +00009#ifndef _CONFIG_EB_CPU5282_H_
10#define _CONFIG_EB_CPU5282_H_
Heiko Schocherac1956e2006-04-20 08:42:42 +020011
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020012#undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP
Wolfgang Denkf7290752006-06-10 22:00:40 +020013
Jens Scharsig772d9b02009-07-24 10:31:48 +020014/*----------------------------------------------------------------------*
15 * High Level Configuration Options (easy to change) *
16 *----------------------------------------------------------------------*/
Heiko Schocherac1956e2006-04-20 08:42:42 +020017
Heiko Schocherac1956e2006-04-20 08:42:42 +020018#define CONFIG_MISC_INIT_R
19
TsiChungLiewceaf3332007-08-15 19:55:10 -050020#define CONFIG_MCFUART
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020021#define CONFIG_SYS_UART_PORT (0)
Heiko Schocherac1956e2006-04-20 08:42:42 +020022
Jens Scharsig772d9b02009-07-24 10:31:48 +020023#undef CONFIG_MONITOR_IS_IN_RAM /* starts uboot direct */
Heiko Schocherac1956e2006-04-20 08:42:42 +020024
25#define CONFIG_BOOTCOMMAND "printenv"
26
Jens Scharsig772d9b02009-07-24 10:31:48 +020027/*----------------------------------------------------------------------*
28 * Options *
29 *----------------------------------------------------------------------*/
30
31#define CONFIG_BOOT_RETRY_TIME -1
32#define CONFIG_RESET_TO_RETRY
33#define CONFIG_SPLASH_SCREEN
34
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +000035#define CONFIG_HW_WATCHDOG
36
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +000037#define STATUS_LED_ACTIVE 0
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +000038
Jens Scharsig772d9b02009-07-24 10:31:48 +020039/*----------------------------------------------------------------------*
40 * Configuration for environment *
41 * Environment is in the second sector of the first 256k of flash *
42 *----------------------------------------------------------------------*/
43
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +000044#define CONFIG_ENV_ADDR 0xFF040000
45#define CONFIG_ENV_SECT_SIZE 0x00020000
Heiko Schocherac1956e2006-04-20 08:42:42 +020046
Jon Loeligerdbb2b542007-07-07 20:56:05 -050047/*
Jon Loeligerf5709d12007-07-10 09:02:57 -050048 * BOOTP options
49 */
50#define CONFIG_BOOTP_BOOTFILESIZE
51#define CONFIG_BOOTP_BOOTPATH
52#define CONFIG_BOOTP_GATEWAY
53#define CONFIG_BOOTP_HOSTNAME
54
Jon Loeligerf5709d12007-07-10 09:02:57 -050055/*
Jon Loeligerdbb2b542007-07-07 20:56:05 -050056 * Command line configuration.
57 */
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +000058#define CONFIG_CMDLINE_EDITING
Jon Loeligerdbb2b542007-07-07 20:56:05 -050059
TsiChung Liew26c9f3c2008-07-09 15:21:44 -050060#define CONFIG_MCFTMR
61
Jens Scharsig772d9b02009-07-24 10:31:48 +020062#define CONFIG_SYS_LONGHELP 1
Heiko Schocherac1956e2006-04-20 08:42:42 +020063
Jens Scharsig772d9b02009-07-24 10:31:48 +020064#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Jens Scharsig772d9b02009-07-24 10:31:48 +020065#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
66#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
67#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Heiko Schocherac1956e2006-04-20 08:42:42 +020068
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020069#define CONFIG_SYS_LOAD_ADDR 0x20000
Heiko Schocherac1956e2006-04-20 08:42:42 +020070
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020071#define CONFIG_SYS_MEMTEST_START 0x100000
72#define CONFIG_SYS_MEMTEST_END 0x400000
73/*#define CONFIG_SYS_DRAM_TEST 1 */
74#undef CONFIG_SYS_DRAM_TEST
Heiko Schocherac1956e2006-04-20 08:42:42 +020075
Jens Scharsig772d9b02009-07-24 10:31:48 +020076/*----------------------------------------------------------------------*
77 * Clock and PLL Configuration *
78 *----------------------------------------------------------------------*/
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +000079#define CONFIG_SYS_CLK 80000000 /* 8MHz * 8 */
Heiko Schocherac1956e2006-04-20 08:42:42 +020080
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +000081/* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */
Heiko Schocherac1956e2006-04-20 08:42:42 +020082
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +000083#define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */
Jens Scharsig772d9b02009-07-24 10:31:48 +020084#define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
Heiko Schocherac1956e2006-04-20 08:42:42 +020085
Jens Scharsig772d9b02009-07-24 10:31:48 +020086/*----------------------------------------------------------------------*
87 * Network *
88 *----------------------------------------------------------------------*/
89
90#define CONFIG_MCFFEC
Jens Scharsig772d9b02009-07-24 10:31:48 +020091#define CONFIG_MII 1
92#define CONFIG_MII_INIT 1
93#define CONFIG_SYS_DISCOVER_PHY
94#define CONFIG_SYS_RX_ETH_BUFFER 8
95#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
96
97#define CONFIG_SYS_FEC0_PINMUX 0
98#define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
99#define MCFFEC_TOUT_LOOP 50000
100
Jens Scharsig772d9b02009-07-24 10:31:48 +0200101#define CONFIG_OVERWRITE_ETHADDR_ONCE
102
103/*-------------------------------------------------------------------------
Heiko Schocherac1956e2006-04-20 08:42:42 +0200104 * Low Level Configuration Settings
105 * (address mappings, register initial values, etc.)
106 * You should know what you are doing if you make changes here.
Jens Scharsig772d9b02009-07-24 10:31:48 +0200107 *-----------------------------------------------------------------------*/
108
109#define CONFIG_SYS_MBAR 0x40000000
Heiko Schocherac1956e2006-04-20 08:42:42 +0200110
Heiko Schocherac1956e2006-04-20 08:42:42 +0200111/*-----------------------------------------------------------------------
112 * Definitions for initial stack pointer and data area (in DPRAM)
Jens Scharsig772d9b02009-07-24 10:31:48 +0200113 *-----------------------------------------------------------------------*/
114
115#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +0000116#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
Jens Scharsig772d9b02009-07-24 10:31:48 +0200117#define CONFIG_SYS_GBL_DATA_OFFSET \
Wolfgang Denk0191e472010-10-26 14:34:52 +0200118 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200119#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Heiko Schocherac1956e2006-04-20 08:42:42 +0200120
121/*-----------------------------------------------------------------------
122 * Start addresses for the final memory configuration
123 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200124 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
Heiko Schocherac1956e2006-04-20 08:42:42 +0200125 */
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +0000126#define CONFIG_SYS_SDRAM_BASE0 0x00000000
127#define CONFIG_SYS_SDRAM_SIZE0 16 /* SDRAM size in MB */
Heiko Schocherac1956e2006-04-20 08:42:42 +0200128
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +0000129#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE0
130#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE0
Heiko Schocherac1956e2006-04-20 08:42:42 +0200131
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200132#define CONFIG_SYS_MONITOR_LEN 0x20000
Jens Scharsig (BuS Elektronik)ef1030c2013-09-23 08:26:41 +0200133#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200134#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
Heiko Schocherac1956e2006-04-20 08:42:42 +0200135
136/*
137 * For booting Linux, the board info and command line data
138 * have to be in the first 8 MB of memory, since this is
139 * the maximum mapped by the Linux kernel during initialization ??
140 */
Jens Scharsig772d9b02009-07-24 10:31:48 +0200141#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Heiko Schocherac1956e2006-04-20 08:42:42 +0200142
143/*-----------------------------------------------------------------------
144 * FLASH organization
145 */
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +0000146#define CONFIG_FLASH_SHOW_PROGRESS 45
Jens Scharsig772d9b02009-07-24 10:31:48 +0200147
148#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
149#define CONFIG_SYS_INT_FLASH_BASE 0xF0000000
150#define CONFIG_SYS_INT_FLASH_ENABLE 0x21
151
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +0000152#define CONFIG_SYS_MAX_FLASH_SECT 128
153#define CONFIG_SYS_MAX_FLASH_BANKS 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200154#define CONFIG_SYS_FLASH_ERASE_TOUT 10000000
155#define CONFIG_SYS_FLASH_PROTECTION
Heiko Schocherac1956e2006-04-20 08:42:42 +0200156
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +0000157#define CONFIG_SYS_FLASH_CFI
158#define CONFIG_FLASH_CFI_DRIVER
159#define CONFIG_SYS_FLASH_SIZE 16*1024*1024
160#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
161
162#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
163
Heiko Schocherac1956e2006-04-20 08:42:42 +0200164/*-----------------------------------------------------------------------
165 * Cache Configuration
166 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200167#define CONFIG_SYS_CACHELINE_SIZE 16
Heiko Schocherac1956e2006-04-20 08:42:42 +0200168
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600169#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200170 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600171#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200172 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600173#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
174#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
175 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
176 CF_ACR_EN | CF_ACR_SM_ALL)
177#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
178 CF_CACR_CEIB | CF_CACR_DBWE | \
179 CF_CACR_EUSP)
180
Heiko Schocherac1956e2006-04-20 08:42:42 +0200181/*-----------------------------------------------------------------------
182 * Memory bank definitions
183 */
184
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +0000185#define CONFIG_SYS_CS0_BASE 0xFF000000
TsiChung Liew7f1a0462008-10-21 10:03:07 +0000186#define CONFIG_SYS_CS0_CTRL 0x00001980
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +0000187#define CONFIG_SYS_CS0_MASK 0x00FF0001
Heiko Schocherac1956e2006-04-20 08:42:42 +0200188
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +0000189#define CONFIG_SYS_CS2_BASE 0xE0000000
190#define CONFIG_SYS_CS2_CTRL 0x00001980
191#define CONFIG_SYS_CS2_MASK 0x000F0001
192
193#define CONFIG_SYS_CS3_BASE 0xE0100000
194#define CONFIG_SYS_CS3_CTRL 0x00001980
TsiChung Liew7f1a0462008-10-21 10:03:07 +0000195#define CONFIG_SYS_CS3_MASK 0x000F0001
Heiko Schocherac1956e2006-04-20 08:42:42 +0200196
197/*-----------------------------------------------------------------------
198 * Port configuration
199 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200200#define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */
201#define CONFIG_SYS_PADDR 0x0000000
202#define CONFIG_SYS_PADAT 0x0000000
Heiko Schocherac1956e2006-04-20 08:42:42 +0200203
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200204#define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */
205#define CONFIG_SYS_PBDDR 0x0000000
206#define CONFIG_SYS_PBDAT 0x0000000
Heiko Schocherac1956e2006-04-20 08:42:42 +0200207
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200208#define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */
209#define CONFIG_SYS_PCDDR 0x0000000
210#define CONFIG_SYS_PCDAT 0x0000000
Heiko Schocherac1956e2006-04-20 08:42:42 +0200211
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200212#define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */
213#define CONFIG_SYS_PCDDR 0x0000000
214#define CONFIG_SYS_PCDAT 0x0000000
Heiko Schocherac1956e2006-04-20 08:42:42 +0200215
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +0000216#define CONFIG_SYS_PASPAR 0x0F0F
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200217#define CONFIG_SYS_PEHLPAR 0xC0
Jens Scharsig772d9b02009-07-24 10:31:48 +0200218#define CONFIG_SYS_PUAPAR 0x0F
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200219#define CONFIG_SYS_DDRUA 0x05
220#define CONFIG_SYS_PJPAR 0xFF
Heiko Schocherac1956e2006-04-20 08:42:42 +0200221
222/*-----------------------------------------------------------------------
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +0000223 * I2C
224 */
225
Heiko Schocherf2850742012-10-24 13:48:22 +0200226#define CONFIG_SYS_I2C
227#define CONFIG_SYS_I2C_FSL
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +0000228
Heiko Schocherf2850742012-10-24 13:48:22 +0200229#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +0000230#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
231
Heiko Schocherf2850742012-10-24 13:48:22 +0200232#define CONFIG_SYS_FSL_I2C_SPEED 100000
233#define CONFIG_SYS_FSL_I2C_SLAVE 0
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +0000234
235#ifdef CONFIG_CMD_DATE
236#define CONFIG_RTC_DS1338
237#define CONFIG_I2C_RTC_ADDR 0x68
238#endif
239
240/*-----------------------------------------------------------------------
Jens Scharsig772d9b02009-07-24 10:31:48 +0200241 * VIDEO configuration
Heiko Schocherac1956e2006-04-20 08:42:42 +0200242 */
243
Jens Scharsig772d9b02009-07-24 10:31:48 +0200244#ifdef CONFIG_VIDEO
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +0000245#define CONFIG_VIDEO_VCXK 1
Jens Scharsig772d9b02009-07-24 10:31:48 +0200246
247#define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 2
248#define CONFIG_SYS_VCXK_DOUBLEBUFFERED 1
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +0000249#define CONFIG_SYS_VCXK_BASE CONFIG_SYS_CS2_BASE
Jens Scharsig772d9b02009-07-24 10:31:48 +0200250
251#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT MCFGPTB_GPTPORT
252#define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR
253#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN 0x0001
254
255#define CONFIG_SYS_VCXK_ENABLE_PORT MCFGPTB_GPTPORT
256#define CONFIG_SYS_VCXK_ENABLE_DDR MCFGPTB_GPTDDR
257#define CONFIG_SYS_VCXK_ENABLE_PIN 0x0002
258
259#define CONFIG_SYS_VCXK_REQUEST_PORT MCFGPTB_GPTPORT
260#define CONFIG_SYS_VCXK_REQUEST_DDR MCFGPTB_GPTDDR
261#define CONFIG_SYS_VCXK_REQUEST_PIN 0x0004
262
263#define CONFIG_SYS_VCXK_INVERT_PORT MCFGPIO_PORTE
264#define CONFIG_SYS_VCXK_INVERT_DDR MCFGPIO_DDRE
265#define CONFIG_SYS_VCXK_INVERT_PIN MCFGPIO_PORT2
Heiko Schocherac1956e2006-04-20 08:42:42 +0200266
Jens Scharsig772d9b02009-07-24 10:31:48 +0200267#endif /* CONFIG_VIDEO */
Heiko Schocherac1956e2006-04-20 08:42:42 +0200268#endif /* _CONFIG_M5282EVB_H */
269/*---------------------------------------------------------------------*/