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git01.mediatek.com / filogic / uboot / da92c9762cc517cad19421fa310814ddf987a574 / . / include / configs / tegra114-common.h
blob: 75d2065177a12f215ff94b482f978a379d4ee40b [file] [log] [blame]
Tom Warren7a3fa012013-01-28 13:32:13 +0000[diff] [blame]1/*
2 * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
3 *
Tom Rinie2378802016-01-14 22:05:13 -0500[diff] [blame]4 * SPDX-License-Identifier: GPL-2.0
Tom Warren7a3fa012013-01-28 13:32:13 +0000[diff] [blame]5 */
6
7#ifndef _TEGRA114_COMMON_H_
8#define _TEGRA114_COMMON_H_
9#include "tegra-common.h"
10
11/*
12 * NS16550 Configuration
13 */
14#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
15
Tom Warren7a3fa012013-01-28 13:32:13 +0000[diff] [blame]16/*
17 * Miscellaneous configurable options
18 */
Tom Warren7a3fa012013-01-28 13:32:13 +0000[diff] [blame]19#define CONFIG_STACKBASE 0x82800000 /* 40MB */
20
21/*-----------------------------------------------------------------------
22 * Physical Memory Map
23 */
Stephen Warrenf5bd7452015-09-23 12:34:01 -0600[diff] [blame]24#define CONFIG_SYS_TEXT_BASE 0x80110000
Tom Warren7a3fa012013-01-28 13:32:13 +0000[diff] [blame]25
26/*
27 * Memory layout for where various images get loaded by boot scripts:
28 *
29 * scriptaddr can be pretty much anywhere that doesn't conflict with something
30 * else. Put it above BOOTMAPSZ to eliminate conflicts.
31 *
Stephen Warren7434dfe2014-02-05 09:24:59 -0700[diff] [blame]32 * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
33 * something else. Put it above BOOTMAPSZ to eliminate conflicts.
34 *
Tom Warren7a3fa012013-01-28 13:32:13 +0000[diff] [blame]35 * kernel_addr_r must be within the first 128M of RAM in order for the
36 * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
37 * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
38 * should not overlap that area, or the kernel will have to copy itself
39 * somewhere else before decompression. Similarly, the address of any other
40 * data passed to the kernel shouldn't overlap the start of RAM. Pushing
41 * this up to 16M allows for a sizable kernel to be decompressed below the
42 * compressed load address.
43 *
44 * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
45 * the compressed kernel to be up to 16M too.
46 *
47 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
48 * for the FDT/DTB to be up to 1M, which is hopefully plenty.
49 */
Stephen Warrenf61f1292015-04-01 15:40:53 -0600[diff] [blame]50#define CONFIG_LOADADDR 0x81000000
Tom Warren7a3fa012013-01-28 13:32:13 +0000[diff] [blame]51#define MEM_LAYOUT_ENV_SETTINGS \
52 "scriptaddr=0x90000000\0" \
Stephen Warren7434dfe2014-02-05 09:24:59 -0700[diff] [blame]53 "pxefile_addr_r=0x90100000\0" \
Stephen Warrenf61f1292015-04-01 15:40:53 -0600[diff] [blame]54 "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
Tom Warren7a3fa012013-01-28 13:32:13 +0000[diff] [blame]55 "fdt_addr_r=0x82000000\0" \
56 "ramdisk_addr_r=0x82100000\0"
57
58/* Defines for SPL */
59#define CONFIG_SPL_TEXT_BASE 0x80108000
60#define CONFIG_SYS_SPL_MALLOC_START 0x80090000
61#define CONFIG_SPL_STACK 0x800ffffc
62
Jim Lin68c0c02c2013-06-21 19:05:48 +0800[diff] [blame]63/* For USB EHCI controller */
64#define CONFIG_EHCI_IS_TDI
Jim Lincbb4c5e2013-11-06 14:03:44 +0800[diff] [blame]65#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
Jim Lin68c0c02c2013-06-21 19:05:48 +0800[diff] [blame]66
Tom Warren7a3fa012013-01-28 13:32:13 +0000[diff] [blame]67#endif /* _TEGRA114_COMMON_H_ */