| Peng Fan | b341534 | 2018-10-18 14:28:17 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright 2018 NXP |
| 4 | */ |
| 5 | |
| 6 | #define MIDR_PARTNUM_CORTEX_A35 0xD04 |
| 7 | #define MIDR_PARTNUM_CORTEX_A53 0xD03 |
| 8 | #define MIDR_PARTNUM_CORTEX_A72 0xD08 |
| 9 | #define MIDR_PARTNUM_SHIFT 0x4 |
| 10 | #define MIDR_PARTNUM_MASK (0xFFF << 0x4) |
| 11 | |
| 12 | static inline unsigned int read_midr(void) |
| 13 | { |
| 14 | unsigned long val; |
| 15 | |
| 16 | asm volatile("mrs %0, midr_el1" : "=r" (val)); |
| 17 | |
| 18 | return val; |
| 19 | } |
| 20 | |
| 21 | #define is_cortex_a35() (((read_midr() & MIDR_PARTNUM_MASK) >> \ |
| 22 | MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A35) |
| 23 | #define is_cortex_a53() (((read_midr() & MIDR_PARTNUM_MASK) >> \ |
| 24 | MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A53) |
| 25 | #define is_cortex_a72() (((read_midr() & MIDR_PARTNUM_MASK) >>\ |
| 26 | MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A72) |