| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| Tom Warren | 13ac544 | 2012-12-11 13:34:12 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. |
| Tom Warren | 13ac544 | 2012-12-11 13:34:12 +0000 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef _TEGRA30_H_ |
| 7 | #define _TEGRA30_H_ |
| 8 | |
| Marcel Ziswiler | c5ecf27 | 2014-10-10 23:32:32 +0200 | [diff] [blame] | 9 | #define NV_PA_MC_BASE 0x7000F000 |
| Tom Warren | 13ac544 | 2012-12-11 13:34:12 +0000 | [diff] [blame] | 10 | #define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T30 */ |
| 11 | |
| 12 | #include <asm/arch-tegra/tegra.h> |
| 13 | |
| Lucas Stach | 26c3216 | 2013-02-07 07:16:29 +0000 | [diff] [blame] | 14 | #define TEGRA_USB1_BASE 0x7D000000 |
| 15 | |
| Tom Warren | 13ac544 | 2012-12-11 13:34:12 +0000 | [diff] [blame] | 16 | #define BCT_ODMDATA_OFFSET 6116 /* 12 bytes from end of BCT */ |
| 17 | |
| Tom Warren | 795f9d7 | 2013-01-23 14:01:01 -0700 | [diff] [blame] | 18 | #define MAX_NUM_CPU 4 |
| 19 | |
| Tom Warren | 13ac544 | 2012-12-11 13:34:12 +0000 | [diff] [blame] | 20 | #endif /* TEGRA30_H */ |