blob: 501c4f00c4e03ef9d536eff2e1c1ac0646e2dff6 [file] [log] [blame]
Stephen Warren9e549802015-10-05 12:09:01 -06001/*
2 * (C) Copyright 2014 - 2015 Xilinx, Inc.
3 * Michal Simek <michal.simek@xilinx.com>
4 * (This file derived from arch/arm/cpu/armv8/zynqmp/cpu.c)
5 *
6 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11#include <common.h>
12#include <asm/system.h>
13#include <asm/armv8/mmu.h>
14
Alexander Grafda6cfe12016-03-04 01:09:50 +010015static struct mm_region tegra_mem_map[] = {
16 {
17 .base = 0x0UL,
18 .size = 0x80000000UL,
19 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
20 PTE_BLOCK_NON_SHARE |
21 PTE_BLOCK_PXN | PTE_BLOCK_UXN
22 }, {
23 .base = 0x80000000UL,
24 .size = 0xff80000000UL,
25 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
26 PTE_BLOCK_INNER_SHARE
27 }, {
28 /* List terminator */
29 0,
Stephen Warren9e549802015-10-05 12:09:01 -060030 }
Alexander Grafda6cfe12016-03-04 01:09:50 +010031};
Stephen Warren9e549802015-10-05 12:09:01 -060032
Alexander Grafda6cfe12016-03-04 01:09:50 +010033struct mm_region *mem_map = tegra_mem_map;