Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause |
| 2 | /* |
| 3 | * Copyright (C) 2018, STMicroelectronics - All Rights Reserved |
| 4 | */ |
| 5 | |
| 6 | #include <common.h> |
| 7 | #include <adc.h> |
| 8 | #include <asm/arch/stm32.h> |
| 9 | #include <asm/arch/sys_proto.h> |
| 10 | #include <asm/gpio.h> |
| 11 | #include <asm/io.h> |
| 12 | #include <bootm.h> |
| 13 | #include <clk.h> |
| 14 | #include <config.h> |
| 15 | #include <dm.h> |
| 16 | #include <dm/device.h> |
| 17 | #include <dm/uclass.h> |
| 18 | #include <env.h> |
| 19 | #include <env_internal.h> |
| 20 | #include <g_dnl.h> |
| 21 | #include <generic-phy.h> |
| 22 | #include <hang.h> |
| 23 | #include <i2c.h> |
| 24 | #include <i2c_eeprom.h> |
| 25 | #include <init.h> |
| 26 | #include <led.h> |
| 27 | #include <memalign.h> |
| 28 | #include <misc.h> |
| 29 | #include <mtd.h> |
| 30 | #include <mtd_node.h> |
| 31 | #include <netdev.h> |
| 32 | #include <phy.h> |
| 33 | #include <power/regulator.h> |
| 34 | #include <remoteproc.h> |
| 35 | #include <reset.h> |
| 36 | #include <syscon.h> |
| 37 | #include <usb.h> |
| 38 | #include <usb/dwc2_udc.h> |
| 39 | #include <watchdog.h> |
| 40 | |
| 41 | /* SYSCFG registers */ |
| 42 | #define SYSCFG_BOOTR 0x00 |
| 43 | #define SYSCFG_PMCSETR 0x04 |
| 44 | #define SYSCFG_IOCTRLSETR 0x18 |
| 45 | #define SYSCFG_ICNR 0x1C |
| 46 | #define SYSCFG_CMPCR 0x20 |
| 47 | #define SYSCFG_CMPENSETR 0x24 |
| 48 | #define SYSCFG_PMCCLRR 0x44 |
| 49 | |
| 50 | #define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0) |
| 51 | #define SYSCFG_BOOTR_BOOTPD_SHIFT 4 |
| 52 | |
| 53 | #define SYSCFG_IOCTRLSETR_HSLVEN_TRACE BIT(0) |
| 54 | #define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI BIT(1) |
| 55 | #define SYSCFG_IOCTRLSETR_HSLVEN_ETH BIT(2) |
| 56 | #define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC BIT(3) |
| 57 | #define SYSCFG_IOCTRLSETR_HSLVEN_SPI BIT(4) |
| 58 | |
| 59 | #define SYSCFG_CMPCR_SW_CTRL BIT(1) |
| 60 | #define SYSCFG_CMPCR_READY BIT(8) |
| 61 | |
| 62 | #define SYSCFG_CMPENSETR_MPU_EN BIT(0) |
| 63 | |
| 64 | #define SYSCFG_PMCSETR_ETH_CLK_SEL BIT(16) |
| 65 | #define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17) |
| 66 | |
| 67 | #define SYSCFG_PMCSETR_ETH_SELMII BIT(20) |
| 68 | |
| 69 | #define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21) |
| 70 | #define SYSCFG_PMCSETR_ETH_SEL_GMII_MII 0 |
| 71 | #define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21) |
| 72 | #define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23) |
| 73 | |
| 74 | /* |
| 75 | * Get a global data pointer |
| 76 | */ |
| 77 | DECLARE_GLOBAL_DATA_PTR; |
| 78 | |
| 79 | int setup_mac_address(void) |
| 80 | { |
| 81 | struct udevice *dev; |
| 82 | ofnode eeprom; |
| 83 | unsigned char enetaddr[6]; |
| 84 | int ret; |
| 85 | |
| 86 | ret = eth_env_get_enetaddr("ethaddr", enetaddr); |
| 87 | if (ret) /* ethaddr is already set */ |
| 88 | return 0; |
| 89 | |
| 90 | eeprom = ofnode_path("/soc/i2c@5c002000/eeprom@50"); |
| 91 | if (!ofnode_valid(eeprom)) { |
| 92 | printf("Invalid hardware path to EEPROM!\n"); |
| 93 | return -ENODEV; |
| 94 | } |
| 95 | |
| 96 | ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, eeprom, &dev); |
| 97 | if (ret) { |
| 98 | printf("Cannot find EEPROM!\n"); |
| 99 | return ret; |
| 100 | } |
| 101 | |
| 102 | ret = i2c_eeprom_read(dev, 0xfa, enetaddr, 0x6); |
| 103 | if (ret) { |
| 104 | printf("Error reading configuration EEPROM!\n"); |
| 105 | return ret; |
| 106 | } |
| 107 | |
| 108 | if (is_valid_ethaddr(enetaddr)) |
| 109 | eth_env_set_enetaddr("ethaddr", enetaddr); |
| 110 | |
| 111 | return 0; |
| 112 | } |
| 113 | |
| 114 | int checkboard(void) |
| 115 | { |
| 116 | char *mode; |
| 117 | const char *fdt_compat; |
| 118 | int fdt_compat_len; |
| 119 | |
| 120 | if (IS_ENABLED(CONFIG_STM32MP1_OPTEE)) |
| 121 | mode = "trusted with OP-TEE"; |
| 122 | else if (IS_ENABLED(CONFIG_STM32MP1_TRUSTED)) |
| 123 | mode = "trusted"; |
| 124 | else |
| 125 | mode = "basic"; |
| 126 | |
| 127 | printf("Board: stm32mp1 in %s mode", mode); |
| 128 | fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible", |
| 129 | &fdt_compat_len); |
| 130 | if (fdt_compat && fdt_compat_len) |
| 131 | printf(" (%s)", fdt_compat); |
| 132 | puts("\n"); |
| 133 | |
| 134 | return 0; |
| 135 | } |
| 136 | |
| 137 | static void board_key_check(void) |
| 138 | { |
| 139 | #if defined(CONFIG_FASTBOOT) || defined(CONFIG_CMD_STM32PROG) |
| 140 | ofnode node; |
| 141 | struct gpio_desc gpio; |
| 142 | enum forced_boot_mode boot_mode = BOOT_NORMAL; |
| 143 | |
| 144 | node = ofnode_path("/config"); |
| 145 | if (!ofnode_valid(node)) { |
| 146 | debug("%s: no /config node?\n", __func__); |
| 147 | return; |
| 148 | } |
| 149 | #ifdef CONFIG_FASTBOOT |
| 150 | if (gpio_request_by_name_nodev(node, "st,fastboot-gpios", 0, |
| 151 | &gpio, GPIOD_IS_IN)) { |
| 152 | debug("%s: could not find a /config/st,fastboot-gpios\n", |
| 153 | __func__); |
| 154 | } else { |
| 155 | if (dm_gpio_get_value(&gpio)) { |
| 156 | puts("Fastboot key pressed, "); |
| 157 | boot_mode = BOOT_FASTBOOT; |
| 158 | } |
| 159 | |
| 160 | dm_gpio_free(NULL, &gpio); |
| 161 | } |
| 162 | #endif |
| 163 | #ifdef CONFIG_CMD_STM32PROG |
| 164 | if (gpio_request_by_name_nodev(node, "st,stm32prog-gpios", 0, |
| 165 | &gpio, GPIOD_IS_IN)) { |
| 166 | debug("%s: could not find a /config/st,stm32prog-gpios\n", |
| 167 | __func__); |
| 168 | } else { |
| 169 | if (dm_gpio_get_value(&gpio)) { |
| 170 | puts("STM32Programmer key pressed, "); |
| 171 | boot_mode = BOOT_STM32PROG; |
| 172 | } |
| 173 | dm_gpio_free(NULL, &gpio); |
| 174 | } |
| 175 | #endif |
| 176 | |
| 177 | if (boot_mode != BOOT_NORMAL) { |
| 178 | puts("entering download mode...\n"); |
| 179 | clrsetbits_le32(TAMP_BOOT_CONTEXT, |
| 180 | TAMP_BOOT_FORCED_MASK, |
| 181 | boot_mode); |
| 182 | } |
| 183 | #endif |
| 184 | } |
| 185 | |
| 186 | #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) |
| 187 | |
| 188 | #include <usb/dwc2_udc.h> |
| 189 | int g_dnl_board_usb_cable_connected(void) |
| 190 | { |
| 191 | struct udevice *dwc2_udc_otg; |
| 192 | int ret; |
| 193 | |
| 194 | ret = uclass_get_device_by_driver(UCLASS_USB_GADGET_GENERIC, |
| 195 | DM_GET_DRIVER(dwc2_udc_otg), |
| 196 | &dwc2_udc_otg); |
| 197 | if (!ret) |
| 198 | debug("dwc2_udc_otg init failed\n"); |
| 199 | |
| 200 | return dwc2_udc_B_session_valid(dwc2_udc_otg); |
| 201 | } |
| 202 | |
| 203 | #define STM32MP1_G_DNL_DFU_PRODUCT_NUM 0xdf11 |
| 204 | #define STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM 0x0afb |
| 205 | |
| 206 | int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) |
| 207 | { |
| 208 | if (!strcmp(name, "usb_dnl_dfu")) |
| 209 | put_unaligned(STM32MP1_G_DNL_DFU_PRODUCT_NUM, &dev->idProduct); |
| 210 | else if (!strcmp(name, "usb_dnl_fastboot")) |
| 211 | put_unaligned(STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM, |
| 212 | &dev->idProduct); |
| 213 | else |
| 214 | put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM, &dev->idProduct); |
| 215 | |
| 216 | return 0; |
| 217 | } |
| 218 | |
| 219 | #endif /* CONFIG_USB_GADGET */ |
| 220 | |
| 221 | #ifdef CONFIG_LED |
| 222 | static int get_led(struct udevice **dev, char *led_string) |
| 223 | { |
| 224 | char *led_name; |
| 225 | int ret; |
| 226 | |
| 227 | led_name = fdtdec_get_config_string(gd->fdt_blob, led_string); |
| 228 | if (!led_name) { |
| 229 | pr_debug("%s: could not find %s config string\n", |
| 230 | __func__, led_string); |
| 231 | return -ENOENT; |
| 232 | } |
| 233 | ret = led_get_by_label(led_name, dev); |
| 234 | if (ret) { |
| 235 | debug("%s: get=%d\n", __func__, ret); |
| 236 | return ret; |
| 237 | } |
| 238 | |
| 239 | return 0; |
| 240 | } |
| 241 | |
| 242 | static int setup_led(enum led_state_t cmd) |
| 243 | { |
| 244 | struct udevice *dev; |
| 245 | int ret; |
| 246 | |
| 247 | ret = get_led(&dev, "u-boot,boot-led"); |
| 248 | if (ret) |
| 249 | return ret; |
| 250 | |
| 251 | ret = led_set_state(dev, cmd); |
| 252 | return ret; |
| 253 | } |
| 254 | #endif |
| 255 | |
| 256 | static void __maybe_unused led_error_blink(u32 nb_blink) |
| 257 | { |
| 258 | #ifdef CONFIG_LED |
| 259 | int ret; |
| 260 | struct udevice *led; |
| 261 | u32 i; |
| 262 | #endif |
| 263 | |
| 264 | if (!nb_blink) |
| 265 | return; |
| 266 | |
| 267 | #ifdef CONFIG_LED |
| 268 | ret = get_led(&led, "u-boot,error-led"); |
| 269 | if (!ret) { |
| 270 | /* make u-boot,error-led blinking */ |
| 271 | /* if U32_MAX and 125ms interval, for 17.02 years */ |
| 272 | for (i = 0; i < 2 * nb_blink; i++) { |
| 273 | led_set_state(led, LEDST_TOGGLE); |
| 274 | mdelay(125); |
| 275 | WATCHDOG_RESET(); |
| 276 | } |
| 277 | } |
| 278 | #endif |
| 279 | |
| 280 | /* infinite: the boot process must be stopped */ |
| 281 | if (nb_blink == U32_MAX) |
| 282 | hang(); |
| 283 | } |
| 284 | |
| 285 | static void sysconf_init(void) |
| 286 | { |
| 287 | #ifndef CONFIG_STM32MP1_TRUSTED |
| 288 | u8 *syscfg; |
| 289 | #ifdef CONFIG_DM_REGULATOR |
| 290 | struct udevice *pwr_dev; |
| 291 | struct udevice *pwr_reg; |
| 292 | struct udevice *dev; |
| 293 | int ret; |
| 294 | u32 otp = 0; |
| 295 | #endif |
| 296 | u32 bootr; |
| 297 | |
| 298 | syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG); |
| 299 | |
| 300 | /* interconnect update : select master using the port 1 */ |
| 301 | /* LTDC = AXI_M9 */ |
| 302 | /* GPU = AXI_M8 */ |
| 303 | /* today information is hardcoded in U-Boot */ |
| 304 | writel(BIT(9), syscfg + SYSCFG_ICNR); |
| 305 | |
| 306 | /* disable Pull-Down for boot pin connected to VDD */ |
| 307 | bootr = readl(syscfg + SYSCFG_BOOTR); |
| 308 | bootr &= ~(SYSCFG_BOOTR_BOOT_MASK << SYSCFG_BOOTR_BOOTPD_SHIFT); |
| 309 | bootr |= (bootr & SYSCFG_BOOTR_BOOT_MASK) << SYSCFG_BOOTR_BOOTPD_SHIFT; |
| 310 | writel(bootr, syscfg + SYSCFG_BOOTR); |
| 311 | |
| 312 | #ifdef CONFIG_DM_REGULATOR |
| 313 | /* High Speed Low Voltage Pad mode Enable for SPI, SDMMC, ETH, QSPI |
| 314 | * and TRACE. Needed above ~50MHz and conditioned by AFMUX selection. |
| 315 | * The customer will have to disable this for low frequencies |
| 316 | * or if AFMUX is selected but the function not used, typically for |
| 317 | * TRACE. Otherwise, impact on power consumption. |
| 318 | * |
| 319 | * WARNING: |
| 320 | * enabling High Speed mode while VDD>2.7V |
| 321 | * with the OTP product_below_2v5 (OTP 18, BIT 13) |
| 322 | * erroneously set to 1 can damage the IC! |
| 323 | * => U-Boot set the register only if VDD < 2.7V (in DT) |
| 324 | * but this value need to be consistent with board design |
| 325 | */ |
| 326 | ret = uclass_get_device_by_driver(UCLASS_PMIC, |
| 327 | DM_GET_DRIVER(stm32mp_pwr_pmic), |
| 328 | &pwr_dev); |
| 329 | if (!ret) { |
| 330 | ret = uclass_get_device_by_driver(UCLASS_MISC, |
| 331 | DM_GET_DRIVER(stm32mp_bsec), |
| 332 | &dev); |
| 333 | if (ret) { |
| 334 | pr_err("Can't find stm32mp_bsec driver\n"); |
| 335 | return; |
| 336 | } |
| 337 | |
| 338 | ret = misc_read(dev, STM32_BSEC_SHADOW(18), &otp, 4); |
| 339 | if (ret > 0) |
| 340 | otp = otp & BIT(13); |
| 341 | |
| 342 | /* get VDD = vdd-supply */ |
| 343 | ret = device_get_supply_regulator(pwr_dev, "vdd-supply", |
| 344 | &pwr_reg); |
| 345 | |
| 346 | /* check if VDD is Low Voltage */ |
| 347 | if (!ret) { |
| 348 | if (regulator_get_value(pwr_reg) < 2700000) { |
| 349 | writel(SYSCFG_IOCTRLSETR_HSLVEN_TRACE | |
| 350 | SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI | |
| 351 | SYSCFG_IOCTRLSETR_HSLVEN_ETH | |
| 352 | SYSCFG_IOCTRLSETR_HSLVEN_SDMMC | |
| 353 | SYSCFG_IOCTRLSETR_HSLVEN_SPI, |
| 354 | syscfg + SYSCFG_IOCTRLSETR); |
| 355 | |
| 356 | if (!otp) |
| 357 | pr_err("product_below_2v5=0: HSLVEN protected by HW\n"); |
| 358 | } else { |
| 359 | if (otp) |
| 360 | pr_err("product_below_2v5=1: HSLVEN update is destructive, no update as VDD>2.7V\n"); |
| 361 | } |
| 362 | } else { |
| 363 | debug("VDD unknown"); |
| 364 | } |
| 365 | } |
| 366 | #endif |
| 367 | |
| 368 | /* activate automatic I/O compensation |
| 369 | * warning: need to ensure CSI enabled and ready in clock driver |
| 370 | */ |
| 371 | writel(SYSCFG_CMPENSETR_MPU_EN, syscfg + SYSCFG_CMPENSETR); |
| 372 | |
| 373 | while (!(readl(syscfg + SYSCFG_CMPCR) & SYSCFG_CMPCR_READY)) |
| 374 | ; |
| 375 | clrbits_le32(syscfg + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL); |
| 376 | #endif |
| 377 | } |
| 378 | |
| 379 | /* board dependent setup after realloc */ |
| 380 | int board_init(void) |
| 381 | { |
| 382 | struct udevice *dev; |
| 383 | |
| 384 | /* address of boot parameters */ |
| 385 | gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100; |
| 386 | |
| 387 | /* probe all PINCTRL for hog */ |
| 388 | for (uclass_first_device(UCLASS_PINCTRL, &dev); |
| 389 | dev; |
| 390 | uclass_next_device(&dev)) { |
| 391 | pr_debug("probe pincontrol = %s\n", dev->name); |
| 392 | } |
| 393 | |
| 394 | board_key_check(); |
| 395 | |
| 396 | #ifdef CONFIG_DM_REGULATOR |
| 397 | regulators_enable_boot_on(_DEBUG); |
| 398 | #endif |
| 399 | |
| 400 | sysconf_init(); |
| 401 | |
| 402 | if (CONFIG_IS_ENABLED(CONFIG_LED)) |
| 403 | led_default_state(); |
| 404 | |
| 405 | return 0; |
| 406 | } |
| 407 | |
| 408 | int board_late_init(void) |
| 409 | { |
| 410 | char *boot_device; |
| 411 | #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
| 412 | const void *fdt_compat; |
| 413 | int fdt_compat_len; |
| 414 | |
| 415 | fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible", |
| 416 | &fdt_compat_len); |
| 417 | if (fdt_compat && fdt_compat_len) { |
| 418 | if (strncmp(fdt_compat, "st,", 3) != 0) |
| 419 | env_set("board_name", fdt_compat); |
| 420 | else |
| 421 | env_set("board_name", fdt_compat + 3); |
| 422 | } |
| 423 | #endif |
| 424 | |
| 425 | /* Check the boot-source to disable bootdelay */ |
| 426 | boot_device = env_get("boot_device"); |
| 427 | if (!strcmp(boot_device, "serial") || !strcmp(boot_device, "usb")) |
| 428 | env_set("bootdelay", "0"); |
| 429 | |
| 430 | return 0; |
| 431 | } |
| 432 | |
| 433 | void board_quiesce_devices(void) |
| 434 | { |
| 435 | #ifdef CONFIG_LED |
| 436 | setup_led(LEDST_OFF); |
| 437 | #endif |
| 438 | } |
| 439 | |
| 440 | /* eth init function : weak called in eqos driver */ |
| 441 | int board_interface_eth_init(struct udevice *dev, |
| 442 | phy_interface_t interface_type) |
| 443 | { |
| 444 | u8 *syscfg; |
| 445 | u32 value; |
| 446 | bool eth_clk_sel_reg = false; |
| 447 | bool eth_ref_clk_sel_reg = false; |
| 448 | |
| 449 | /* Gigabit Ethernet 125MHz clock selection. */ |
| 450 | eth_clk_sel_reg = dev_read_bool(dev, "st,eth_clk_sel"); |
| 451 | |
| 452 | /* Ethernet 50Mhz RMII clock selection */ |
| 453 | eth_ref_clk_sel_reg = |
| 454 | dev_read_bool(dev, "st,eth_ref_clk_sel"); |
| 455 | |
| 456 | syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG); |
| 457 | |
| 458 | if (!syscfg) |
| 459 | return -ENODEV; |
| 460 | |
| 461 | switch (interface_type) { |
| 462 | case PHY_INTERFACE_MODE_MII: |
| 463 | value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII | |
| 464 | SYSCFG_PMCSETR_ETH_REF_CLK_SEL; |
| 465 | debug("%s: PHY_INTERFACE_MODE_MII\n", __func__); |
| 466 | break; |
| 467 | case PHY_INTERFACE_MODE_GMII: |
| 468 | if (eth_clk_sel_reg) |
| 469 | value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII | |
| 470 | SYSCFG_PMCSETR_ETH_CLK_SEL; |
| 471 | else |
| 472 | value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII; |
| 473 | debug("%s: PHY_INTERFACE_MODE_GMII\n", __func__); |
| 474 | break; |
| 475 | case PHY_INTERFACE_MODE_RMII: |
| 476 | if (eth_ref_clk_sel_reg) |
| 477 | value = SYSCFG_PMCSETR_ETH_SEL_RMII | |
| 478 | SYSCFG_PMCSETR_ETH_REF_CLK_SEL; |
| 479 | else |
| 480 | value = SYSCFG_PMCSETR_ETH_SEL_RMII; |
| 481 | debug("%s: PHY_INTERFACE_MODE_RMII\n", __func__); |
| 482 | break; |
| 483 | case PHY_INTERFACE_MODE_RGMII: |
| 484 | case PHY_INTERFACE_MODE_RGMII_ID: |
| 485 | case PHY_INTERFACE_MODE_RGMII_RXID: |
| 486 | case PHY_INTERFACE_MODE_RGMII_TXID: |
| 487 | if (eth_clk_sel_reg) |
| 488 | value = SYSCFG_PMCSETR_ETH_SEL_RGMII | |
| 489 | SYSCFG_PMCSETR_ETH_CLK_SEL; |
| 490 | else |
| 491 | value = SYSCFG_PMCSETR_ETH_SEL_RGMII; |
| 492 | debug("%s: PHY_INTERFACE_MODE_RGMII\n", __func__); |
| 493 | break; |
| 494 | default: |
| 495 | debug("%s: Do not manage %d interface\n", |
| 496 | __func__, interface_type); |
| 497 | /* Do not manage others interfaces */ |
| 498 | return -EINVAL; |
| 499 | } |
| 500 | |
| 501 | /* clear and set ETH configuration bits */ |
| 502 | writel(SYSCFG_PMCSETR_ETH_SEL_MASK | SYSCFG_PMCSETR_ETH_SELMII | |
| 503 | SYSCFG_PMCSETR_ETH_REF_CLK_SEL | SYSCFG_PMCSETR_ETH_CLK_SEL, |
| 504 | syscfg + SYSCFG_PMCCLRR); |
| 505 | writel(value, syscfg + SYSCFG_PMCSETR); |
| 506 | |
| 507 | return 0; |
| 508 | } |
| 509 | |
| 510 | enum env_location env_get_location(enum env_operation op, int prio) |
| 511 | { |
| 512 | if (prio) |
| 513 | return ENVL_UNKNOWN; |
| 514 | |
| 515 | #ifdef CONFIG_ENV_IS_IN_SPI_FLASH |
| 516 | return ENVL_SPI_FLASH; |
| 517 | #else |
| 518 | return ENVL_NOWHERE; |
| 519 | #endif |
| 520 | } |
| 521 | |
| 522 | #ifdef CONFIG_SYS_MTDPARTS_RUNTIME |
| 523 | |
| 524 | #define MTDPARTS_LEN 256 |
| 525 | #define MTDIDS_LEN 128 |
| 526 | |
| 527 | /** |
| 528 | * The mtdparts_nand0 and mtdparts_nor0 variable tends to be long. |
| 529 | * If we need to access it before the env is relocated, then we need |
| 530 | * to use our own stack buffer. gd->env_buf will be too small. |
| 531 | * |
| 532 | * @param buf temporary buffer pointer MTDPARTS_LEN long |
| 533 | * @return mtdparts variable string, NULL if not found |
| 534 | */ |
| 535 | static const char *env_get_mtdparts(const char *str, char *buf) |
| 536 | { |
| 537 | if (gd->flags & GD_FLG_ENV_READY) |
| 538 | return env_get(str); |
| 539 | if (env_get_f(str, buf, MTDPARTS_LEN) != -1) |
| 540 | return buf; |
| 541 | |
| 542 | return NULL; |
| 543 | } |
| 544 | |
| 545 | /** |
| 546 | * update the variables "mtdids" and "mtdparts" with content of mtdparts_<dev> |
| 547 | */ |
| 548 | static void board_get_mtdparts(const char *dev, |
| 549 | char *mtdids, |
| 550 | char *mtdparts) |
| 551 | { |
| 552 | char env_name[32] = "mtdparts_"; |
| 553 | char tmp_mtdparts[MTDPARTS_LEN]; |
| 554 | const char *tmp; |
| 555 | |
| 556 | /* name of env variable to read = mtdparts_<dev> */ |
| 557 | strcat(env_name, dev); |
| 558 | tmp = env_get_mtdparts(env_name, tmp_mtdparts); |
| 559 | if (tmp) { |
| 560 | /* mtdids: "<dev>=<dev>, ...." */ |
| 561 | if (mtdids[0] != '\0') |
| 562 | strcat(mtdids, ","); |
| 563 | strcat(mtdids, dev); |
| 564 | strcat(mtdids, "="); |
| 565 | strcat(mtdids, dev); |
| 566 | |
| 567 | /* mtdparts: "mtdparts=<dev>:<mtdparts_<dev>>;..." */ |
| 568 | if (mtdparts[0] != '\0') |
| 569 | strncat(mtdparts, ";", MTDPARTS_LEN); |
| 570 | else |
| 571 | strcat(mtdparts, "mtdparts="); |
| 572 | strncat(mtdparts, dev, MTDPARTS_LEN); |
| 573 | strncat(mtdparts, ":", MTDPARTS_LEN); |
| 574 | strncat(mtdparts, tmp, MTDPARTS_LEN); |
| 575 | } |
| 576 | } |
| 577 | |
| 578 | void board_mtdparts_default(const char **mtdids, const char **mtdparts) |
| 579 | { |
| 580 | struct udevice *dev; |
| 581 | static char parts[3 * MTDPARTS_LEN + 1]; |
| 582 | static char ids[MTDIDS_LEN + 1]; |
| 583 | static bool mtd_initialized; |
| 584 | |
| 585 | if (mtd_initialized) { |
| 586 | *mtdids = ids; |
| 587 | *mtdparts = parts; |
| 588 | return; |
| 589 | } |
| 590 | |
| 591 | memset(parts, 0, sizeof(parts)); |
| 592 | memset(ids, 0, sizeof(ids)); |
| 593 | |
| 594 | /* probe all MTD devices */ |
| 595 | for (uclass_first_device(UCLASS_MTD, &dev); |
| 596 | dev; |
| 597 | uclass_next_device(&dev)) { |
| 598 | pr_debug("mtd device = %s\n", dev->name); |
| 599 | } |
| 600 | |
| 601 | if (!uclass_get_device(UCLASS_SPI_FLASH, 0, &dev)) |
| 602 | board_get_mtdparts("nor0", ids, parts); |
| 603 | |
| 604 | mtd_initialized = true; |
| 605 | *mtdids = ids; |
| 606 | *mtdparts = parts; |
| 607 | debug("%s:mtdids=%s & mtdparts=%s\n", __func__, ids, parts); |
| 608 | } |
| 609 | #endif |
| 610 | |
| 611 | #if defined(CONFIG_OF_BOARD_SETUP) |
| 612 | int ft_board_setup(void *blob, bd_t *bd) |
| 613 | { |
| 614 | return 0; |
| 615 | } |
| 616 | #endif |
| 617 | |
| 618 | #ifdef CONFIG_SET_DFU_ALT_INFO |
| 619 | #define DFU_ALT_BUF_LEN SZ_1K |
| 620 | |
| 621 | static void board_get_alt_info(const char *dev, char *buff) |
| 622 | { |
| 623 | char var_name[32] = "dfu_alt_info_"; |
| 624 | int ret; |
| 625 | |
| 626 | ALLOC_CACHE_ALIGN_BUFFER(char, tmp_alt, DFU_ALT_BUF_LEN); |
| 627 | |
| 628 | /* name of env variable to read = dfu_alt_info_<dev> */ |
| 629 | strcat(var_name, dev); |
| 630 | ret = env_get_f(var_name, tmp_alt, DFU_ALT_BUF_LEN); |
| 631 | if (ret) { |
| 632 | if (buff[0] != '\0') |
| 633 | strcat(buff, "&"); |
| 634 | strncat(buff, tmp_alt, DFU_ALT_BUF_LEN); |
| 635 | } |
| 636 | } |
| 637 | |
| 638 | void set_dfu_alt_info(char *interface, char *devstr) |
| 639 | { |
| 640 | struct udevice *dev; |
| 641 | |
| 642 | ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN); |
| 643 | |
| 644 | if (env_get("dfu_alt_info")) |
| 645 | return; |
| 646 | |
| 647 | memset(buf, 0, sizeof(buf)); |
| 648 | |
| 649 | /* probe all MTD devices */ |
| 650 | mtd_probe_devices(); |
| 651 | |
| 652 | board_get_alt_info("ram", buf); |
| 653 | |
| 654 | if (!uclass_get_device(UCLASS_MMC, 0, &dev)) |
| 655 | board_get_alt_info("mmc0", buf); |
| 656 | |
| 657 | if (!uclass_get_device(UCLASS_MMC, 1, &dev)) |
| 658 | board_get_alt_info("mmc1", buf); |
| 659 | |
| 660 | if (!uclass_get_device(UCLASS_SPI_FLASH, 0, &dev)) |
| 661 | board_get_alt_info("nor0", buf); |
| 662 | |
| 663 | env_set("dfu_alt_info", buf); |
| 664 | puts("DFU alt info setting: done\n"); |
| 665 | } |
| 666 | #endif |
| 667 | |
| 668 | static void board_copro_image_process(ulong fw_image, size_t fw_size) |
| 669 | { |
| 670 | int ret, id = 0; /* Copro id fixed to 0 as only one coproc on mp1 */ |
| 671 | |
| 672 | if (!rproc_is_initialized()) |
| 673 | if (rproc_init()) { |
| 674 | printf("Remote Processor %d initialization failed\n", |
| 675 | id); |
| 676 | return; |
| 677 | } |
| 678 | |
| 679 | ret = rproc_load(id, fw_image, fw_size); |
| 680 | printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n", |
| 681 | id, fw_image, fw_size, ret ? " Failed!" : " Success!"); |
| 682 | |
| 683 | if (!ret) { |
| 684 | rproc_start(id); |
| 685 | env_set("copro_state", "booted"); |
| 686 | } |
| 687 | } |
| 688 | |
| 689 | U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_COPRO, board_copro_image_process); |