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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Stefan Roese05d10b52013-04-17 00:32:43 +00002/*
3 * Copyright (C) 2013 Stefan Roese <sr@denx.de>
4 *
5 * Configuration settings for the ProjectionDesign / Barco
6 * Titanium board.
7 *
8 * Based on mx6qsabrelite.h which is:
9 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
Stefan Roese05d10b52013-04-17 00:32:43 +000010 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
Eric Nelson062772c2013-11-26 17:40:30 -070015#include "mx6_common.h"
Stefan Roese05d10b52013-04-17 00:32:43 +000016
Stefan Roese05d10b52013-04-17 00:32:43 +000017#define CONFIG_MX6Q
Stefan Roese05d10b52013-04-17 00:32:43 +000018
Tom Rinic6e2db42017-01-25 20:42:38 -050019/* Provide the MACH_TYPE value that the vendor kernel requires. */
20#define CONFIG_MACH_TYPE 3769
Stefan Roese05d10b52013-04-17 00:32:43 +000021
Stefan Roese05d10b52013-04-17 00:32:43 +000022/* Size of malloc() pool */
23#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
24
Stefan Roese05d10b52013-04-17 00:32:43 +000025#define CONFIG_MXC_UART
26#define CONFIG_MXC_UART_BASE UART1_BASE
27
28/* I2C Configs */
trem03997412013-09-21 18:13:36 +020029#define CONFIG_SYS_I2C
30#define CONFIG_SYS_I2C_MXC
Albert ARIBAUD \\(3ADEV\\)eb943872015-09-21 22:43:38 +020031#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
32#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
York Sunf1a52162015-03-20 10:20:40 -070033#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
Stefan Roese05d10b52013-04-17 00:32:43 +000034#define CONFIG_SYS_I2C_SPEED 100000
35
36/* MMC Configs */
Stefan Roese05d10b52013-04-17 00:32:43 +000037#define CONFIG_SYS_FSL_ESDHC_ADDR 0
38#define CONFIG_SYS_FSL_USDHC_NUM 1
39
Stefan Roese05d10b52013-04-17 00:32:43 +000040#define CONFIG_FEC_MXC
Stefan Roese05d10b52013-04-17 00:32:43 +000041#define IMX_FEC_BASE ENET_BASE_ADDR
42#define CONFIG_FEC_XCV_TYPE RGMII
43#define CONFIG_FEC_MXC_PHYADDR 4
Stefan Roese05d10b52013-04-17 00:32:43 +000044
45/* USB Configs */
Stefan Roese05d10b52013-04-17 00:32:43 +000046#define CONFIG_MXC_USB_PORT 1
47#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
48#define CONFIG_MXC_USB_FLAGS 0
49
Stefan Roese05d10b52013-04-17 00:32:43 +000050#define CONFIG_SYS_MEMTEST_START 0x10000000
51#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (500 << 20))
52
Mario Six790d8442018-03-28 14:38:20 +020053#define CONFIG_HOSTNAME "titanium"
Stefan Roese05d10b52013-04-17 00:32:43 +000054#define CONFIG_UBI_PART ubi
55#define CONFIG_UBIFS_VOLUME rootfs0
56
Stefan Roese05d10b52013-04-17 00:32:43 +000057#define CONFIG_EXTRA_ENV_SETTINGS \
Mario Six790d8442018-03-28 14:38:20 +020058 "kernel=" CONFIG_HOSTNAME "/uImage\0" \
Stefan Roese05d10b52013-04-17 00:32:43 +000059 "kernel_fs=/boot/uImage\0" \
60 "kernel_addr=11000000\0" \
Mario Six790d8442018-03-28 14:38:20 +020061 "dtb=" CONFIG_HOSTNAME "/" \
62 CONFIG_HOSTNAME ".dtb\0" \
63 "dtb_fs=/boot/" CONFIG_HOSTNAME ".dtb\0" \
Stefan Roese05d10b52013-04-17 00:32:43 +000064 "dtb_addr=12800000\0" \
65 "script=boot.scr\0" \
66 "uimage=uImage\0" \
67 "console=ttymxc0\0" \
68 "baudrate=115200\0" \
69 "fdt_high=0xffffffff\0" \
70 "initrd_high=0xffffffff\0" \
71 "mmcdev=0\0" \
72 "mmcpart=1\0" \
73 "uimage=uImage\0" \
74 "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}" \
75 " ${script}\0" \
76 "bootscript=echo Running bootscript from mmc ...; source\0" \
77 "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
78 "mmcroot=/dev/mmcblk0p2\0" \
79 "mmcargs=setenv bootargs console=${console},${baudrate} " \
80 "root=${mmcroot} rootwait rw\0" \
81 "bootmmc=run mmcargs; fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}" \
82 " ${uimage}; bootm\0" \
83 "addip=setenv bootargs ${bootargs} " \
84 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
85 ":${hostname}:${netdev}:off panic=1\0" \
86 "addcon=setenv bootargs ${bootargs} console=ttymxc0," \
87 "${baudrate}\0" \
88 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
89 "rootpath=/opt/eldk-5.3/armv7a/rootfs-minimal-mtdutils\0" \
90 "nfsargs=setenv bootargs root=/dev/nfs rw " \
91 "nfsroot=${serverip}:${rootpath}\0" \
Mario Six790d8442018-03-28 14:38:20 +020092 "ubifs=" CONFIG_HOSTNAME "/ubifs.img\0" \
Stefan Roese05d10b52013-04-17 00:32:43 +000093 "part=" __stringify(CONFIG_UBI_PART) "\0" \
94 "boot_vol=0\0" \
95 "vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0" \
96 "load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \
97 "update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \
98 " ${filesize}\0" \
99 "upd_ubifs=run load_ubifs update_ubifs\0" \
100 "init_ubi=nand erase.part ubi;ubi part ${part};" \
101 "ubi create ${vol} c800000\0" \
Tom Rini5ad8e112017-10-22 17:55:07 -0400102 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
103 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
Stefan Roese05d10b52013-04-17 00:32:43 +0000104 "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \
105 " addcon addmtd;" \
106 "bootm ${kernel_addr} - ${dtb_addr}\0" \
107 "ubifsargs=set bootargs ubi.mtd=ubi " \
108 "root=ubi:rootfs${boot_vol} rootfstype=ubifs\0" \
109 "ubifs_mount=ubi part ubi;ubifsmount ubi:rootfs${boot_vol}\0" \
110 "ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \
111 "ubifsload ${dtb_addr} ${dtb_fs};\0" \
112 "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \
113 "addmtd;bootm ${kernel_addr} - ${dtb_addr}\0" \
114 "load_kernel=tftp ${kernel_addr} ${kernel}\0" \
115 "load_dtb=tftp ${dtb_addr} ${dtb}\0" \
116 "net_nfs=run load_dtb load_kernel; " \
117 "run nfsargs addip addcon addmtd;" \
118 "bootm ${kernel_addr} - ${dtb_addr}\0" \
119 "delenv=env default -a -f; saveenv; reset\0"
120
121#define CONFIG_BOOTCOMMAND "run nand_ubifs"
122
Stefan Roese05d10b52013-04-17 00:32:43 +0000123/* Physical Memory Map */
Stefan Roese05d10b52013-04-17 00:32:43 +0000124#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
125#define PHYS_SDRAM_SIZE (512 << 20)
126
127#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
128#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
129#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
130
131#define CONFIG_SYS_INIT_SP_OFFSET \
132 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
133#define CONFIG_SYS_INIT_SP_ADDR \
134 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
135
Stefan Roese05d10b52013-04-17 00:32:43 +0000136/* Enable NAND support */
Stefan Roese05d10b52013-04-17 00:32:43 +0000137#ifdef CONFIG_CMD_NAND
138
139/* NAND stuff */
Stefan Roese05d10b52013-04-17 00:32:43 +0000140#define CONFIG_SYS_MAX_NAND_DEVICE 1
141#define CONFIG_SYS_NAND_BASE 0x40000000
142#define CONFIG_SYS_NAND_5_ADDR_CYCLE
143#define CONFIG_SYS_NAND_ONFI_DETECTION
144
145/* DMA stuff, needed for GPMI/MXS NAND support */
Stefan Roese05d10b52013-04-17 00:32:43 +0000146
147/* Environment in NAND */
Stefan Roese05d10b52013-04-17 00:32:43 +0000148
149#else /* CONFIG_CMD_NAND */
150
151/* Environment in MMC */
Stefan Roese05d10b52013-04-17 00:32:43 +0000152#define CONFIG_SYS_MMC_ENV_DEV 0
153
154#endif /* CONFIG_CMD_NAND */
155
156/* UBI/UBIFS config options */
Stefan Roese05d10b52013-04-17 00:32:43 +0000157
Stefan Roese05d10b52013-04-17 00:32:43 +0000158#endif /* __CONFIG_H */