blob: 6669f2f9602af0b6f038c11509cb32e53c930188 [file] [log] [blame]
Wang Huanf0ce7d62014-09-05 13:52:44 +08001/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
Hongbo Zhang4f6e6102016-07-21 18:09:38 +080010#define CONFIG_ARMV7_PSCI_1_0
Wang Dongsheng13d2bb72015-06-04 12:01:09 +080011
Hongbo Zhang912b3812016-07-21 18:09:39 +080012#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
13
Gong Qianyu52de2e52015-10-26 19:47:42 +080014#define CONFIG_SYS_FSL_CLK
Wang Huanf0ce7d62014-09-05 13:52:44 +080015
Wang Huanf0ce7d62014-09-05 13:52:44 +080016#define CONFIG_SKIP_LOWLEVEL_INIT
Wang Huanf0ce7d62014-09-05 13:52:44 +080017
tang yuantian57296e72014-12-17 12:58:05 +080018#define CONFIG_DEEP_SLEEP
tang yuantian57296e72014-12-17 12:58:05 +080019
Wang Huanf0ce7d62014-09-05 13:52:44 +080020/*
21 * Size of malloc() pool
22 */
23#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
24
25#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
26#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
27
Wang Huanf0ce7d62014-09-05 13:52:44 +080028#ifndef __ASSEMBLY__
29unsigned long get_board_sys_clk(void);
30unsigned long get_board_ddr_clk(void);
31#endif
32
Alison Wang34de5e42016-02-02 15:16:23 +080033#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
Alison Wang2145a372014-12-09 17:38:02 +080034#define CONFIG_SYS_CLK_FREQ 100000000
35#define CONFIG_DDR_CLK_FREQ 100000000
36#define CONFIG_QIXIS_I2C_ACCESS
37#else
Wang Huanf0ce7d62014-09-05 13:52:44 +080038#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
39#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
Alison Wang2145a372014-12-09 17:38:02 +080040#endif
Wang Huanf0ce7d62014-09-05 13:52:44 +080041
Alison Wang9da51782014-12-03 15:00:47 +080042#ifdef CONFIG_RAMBOOT_PBL
43#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg
44#endif
45
46#ifdef CONFIG_SD_BOOT
Alison Wang34de5e42016-02-02 15:16:23 +080047#ifdef CONFIG_SD_BOOT_QSPI
48#define CONFIG_SYS_FSL_PBL_RCW \
49 board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
50#else
51#define CONFIG_SYS_FSL_PBL_RCW \
52 board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
53#endif
Alison Wang9da51782014-12-03 15:00:47 +080054#define CONFIG_SPL_FRAMEWORK
Alison Wang9da51782014-12-03 15:00:47 +080055
56#define CONFIG_SPL_TEXT_BASE 0x10000000
57#define CONFIG_SPL_MAX_SIZE 0x1a000
58#define CONFIG_SPL_STACK 0x1001d000
59#define CONFIG_SPL_PAD_TO 0x1c000
60#define CONFIG_SYS_TEXT_BASE 0x82000000
61
tang yuantian57296e72014-12-17 12:58:05 +080062#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
63 CONFIG_SYS_MONITOR_LEN)
Alison Wang9da51782014-12-03 15:00:47 +080064#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
65#define CONFIG_SPL_BSS_START_ADDR 0x80100000
66#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
Alison Wang8af4c5a2015-10-30 22:45:38 +080067#define CONFIG_SYS_MONITOR_LEN 0xc0000
Alison Wang9da51782014-12-03 15:00:47 +080068#endif
69
Alison Wang2145a372014-12-09 17:38:02 +080070#ifdef CONFIG_QSPI_BOOT
Alison Wang27666082017-05-16 10:45:57 +080071#define CONFIG_SYS_TEXT_BASE 0x40100000
Alison Wang34de5e42016-02-02 15:16:23 +080072#endif
73
Alison Wangab98bb52014-12-09 17:38:14 +080074#ifdef CONFIG_NAND_BOOT
75#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
76#define CONFIG_SPL_FRAMEWORK
Alison Wangab98bb52014-12-09 17:38:14 +080077
78#define CONFIG_SPL_TEXT_BASE 0x10000000
79#define CONFIG_SPL_MAX_SIZE 0x1a000
80#define CONFIG_SPL_STACK 0x1001d000
81#define CONFIG_SPL_PAD_TO 0x1c000
82#define CONFIG_SYS_TEXT_BASE 0x82000000
83
84#define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10)
85#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
86#define CONFIG_SYS_NAND_PAGE_SIZE 2048
87#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
88#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
89
90#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
91#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
92#define CONFIG_SPL_BSS_START_ADDR 0x80100000
93#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
94#define CONFIG_SYS_MONITOR_LEN 0x80000
95#endif
96
Wang Huanf0ce7d62014-09-05 13:52:44 +080097#ifndef CONFIG_SYS_TEXT_BASE
Alison Wang4d786e82015-04-21 16:04:38 +080098#define CONFIG_SYS_TEXT_BASE 0x60100000
Wang Huanf0ce7d62014-09-05 13:52:44 +080099#endif
100
101#define CONFIG_NR_DRAM_BANKS 1
102
103#define CONFIG_DDR_SPD
104#define SPD_EEPROM_ADDRESS 0x51
105#define CONFIG_SYS_SPD_BUS_NUM 0
Wang Huanf0ce7d62014-09-05 13:52:44 +0800106
107#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
York Sunba3c0802014-09-11 13:32:07 -0700108#ifndef CONFIG_SYS_FSL_DDR4
York Sunba3c0802014-09-11 13:32:07 -0700109#define CONFIG_SYS_DDR_RAW_TIMING
110#endif
Wang Huanf0ce7d62014-09-05 13:52:44 +0800111#define CONFIG_DIMM_SLOTS_PER_CTLR 1
112#define CONFIG_CHIP_SELECTS_PER_CTRL 4
113
114#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
115#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
116
117#define CONFIG_DDR_ECC
118#ifdef CONFIG_DDR_ECC
119#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
120#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
121#endif
122
Alison Wanga5494fb2014-12-09 17:37:49 +0800123#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
124 !defined(CONFIG_QSPI_BOOT)
Zhao Qiang9fc2f302014-09-26 16:25:32 +0800125#define CONFIG_U_QE
Zhao Qiang82cd8c62017-05-25 09:47:40 +0800126#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
Zhao Qiang9fc2f302014-09-26 16:25:32 +0800127#endif
128
Wang Huanf0ce7d62014-09-05 13:52:44 +0800129/*
130 * IFC Definitions
131 */
Alison Wang34de5e42016-02-02 15:16:23 +0800132#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
Wang Huanf0ce7d62014-09-05 13:52:44 +0800133#define CONFIG_FSL_IFC
134#define CONFIG_SYS_FLASH_BASE 0x60000000
135#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
136
137#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
138#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
139 CSPR_PORT_SIZE_16 | \
140 CSPR_MSEL_NOR | \
141 CSPR_V)
142#define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
143#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
144 + 0x8000000) | \
145 CSPR_PORT_SIZE_16 | \
146 CSPR_MSEL_NOR | \
147 CSPR_V)
148#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
149
150#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
151 CSOR_NOR_TRHZ_80)
152#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
153 FTIM0_NOR_TEADC(0x5) | \
154 FTIM0_NOR_TEAHC(0x5))
155#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
156 FTIM1_NOR_TRAD_NOR(0x1a) | \
157 FTIM1_NOR_TSEQRAD_NOR(0x13))
158#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
159 FTIM2_NOR_TCH(0x4) | \
160 FTIM2_NOR_TWPH(0xe) | \
161 FTIM2_NOR_TWP(0x1c))
162#define CONFIG_SYS_NOR_FTIM3 0
163
164#define CONFIG_FLASH_CFI_DRIVER
165#define CONFIG_SYS_FLASH_CFI
166#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
167#define CONFIG_SYS_FLASH_QUIET_TEST
168#define CONFIG_FLASH_SHOW_PROGRESS 45
169#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
Yuan Yaoda17d1a2014-10-17 15:26:34 +0800170#define CONFIG_SYS_WRITE_SWAPPED_DATA
Wang Huanf0ce7d62014-09-05 13:52:44 +0800171
172#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
173#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
174#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
175#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
176
177#define CONFIG_SYS_FLASH_EMPTY_INFO
178#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
179 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
180
181/*
182 * NAND Flash Definitions
183 */
184#define CONFIG_NAND_FSL_IFC
185
186#define CONFIG_SYS_NAND_BASE 0x7e800000
187#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
188
189#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
190
191#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
192 | CSPR_PORT_SIZE_8 \
193 | CSPR_MSEL_NAND \
194 | CSPR_V)
195#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
196#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
197 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
198 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
199 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
200 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
201 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
202 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
203
204#define CONFIG_SYS_NAND_ONFI_DETECTION
205
206#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
207 FTIM0_NAND_TWP(0x18) | \
208 FTIM0_NAND_TWCHT(0x7) | \
209 FTIM0_NAND_TWH(0xa))
210#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
211 FTIM1_NAND_TWBE(0x39) | \
212 FTIM1_NAND_TRR(0xe) | \
213 FTIM1_NAND_TRP(0x18))
214#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
215 FTIM2_NAND_TREH(0xa) | \
216 FTIM2_NAND_TWHRE(0x1e))
217#define CONFIG_SYS_NAND_FTIM3 0x0
218
219#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
220#define CONFIG_SYS_MAX_NAND_DEVICE 1
Wang Huanf0ce7d62014-09-05 13:52:44 +0800221
222#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
Alison Wang2145a372014-12-09 17:38:02 +0800223#endif
Wang Huanf0ce7d62014-09-05 13:52:44 +0800224
225/*
226 * QIXIS Definitions
227 */
228#define CONFIG_FSL_QIXIS
229
230#ifdef CONFIG_FSL_QIXIS
231#define QIXIS_BASE 0x7fb00000
232#define QIXIS_BASE_PHYS QIXIS_BASE
233#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
234#define QIXIS_LBMAP_SWITCH 6
235#define QIXIS_LBMAP_MASK 0x0f
236#define QIXIS_LBMAP_SHIFT 0
237#define QIXIS_LBMAP_DFLTBANK 0x00
238#define QIXIS_LBMAP_ALTBANK 0x04
Hongbo Zhang4f6e6102016-07-21 18:09:38 +0800239#define QIXIS_PWR_CTL 0x21
240#define QIXIS_PWR_CTL_POWEROFF 0x80
Wang Huanf0ce7d62014-09-05 13:52:44 +0800241#define QIXIS_RST_CTL_RESET 0x44
242#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
243#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
244#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
Hongbo Zhangf253bbd2016-08-19 17:20:31 +0800245#define QIXIS_CTL_SYS 0x5
246#define QIXIS_CTL_SYS_EVTSW_MASK 0x0c
247#define QIXIS_CTL_SYS_EVTSW_IRQ 0x04
248#define QIXIS_RST_FORCE_3 0x45
249#define QIXIS_RST_FORCE_3_PCIESLOT1 0x80
250#define QIXIS_PWR_CTL2 0x21
251#define QIXIS_PWR_CTL2_PCTL 0x2
Wang Huanf0ce7d62014-09-05 13:52:44 +0800252
253#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
254#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
255 CSPR_PORT_SIZE_8 | \
256 CSPR_MSEL_GPCM | \
257 CSPR_V)
258#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
259#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
260 CSOR_NOR_NOR_MODE_AVD_NOR | \
261 CSOR_NOR_TRHZ_80)
262
263/*
264 * QIXIS Timing parameters for IFC GPCM
265 */
266#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \
267 FTIM0_GPCM_TEADC(0xe) | \
268 FTIM0_GPCM_TEAHC(0xe))
269#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \
270 FTIM1_GPCM_TRAD(0x1f))
271#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \
272 FTIM2_GPCM_TCH(0xe) | \
273 FTIM2_GPCM_TWP(0xf0))
274#define CONFIG_SYS_FPGA_FTIM3 0x0
275#endif
276
Alison Wangab98bb52014-12-09 17:38:14 +0800277#if defined(CONFIG_NAND_BOOT)
278#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
279#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
280#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
281#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
282#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
283#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
284#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
285#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
286#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
287#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
288#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
289#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
290#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
291#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
292#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
293#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
294#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
295#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
296#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
297#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
298#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
299#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
300#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
301#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
302#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
303#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
304#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
305#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
306#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
307#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
308#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
309#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
310#else
Wang Huanf0ce7d62014-09-05 13:52:44 +0800311#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
312#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
313#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
314#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
315#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
316#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
317#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
318#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
319#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
320#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
321#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
322#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
323#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
324#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
325#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
326#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
327#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
328#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
329#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
330#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
331#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
332#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
333#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
334#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
335#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
336#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
337#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
338#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
339#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
340#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
341#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
342#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
Alison Wangab98bb52014-12-09 17:38:14 +0800343#endif
Wang Huanf0ce7d62014-09-05 13:52:44 +0800344
345/*
346 * Serial Port
347 */
Alison Wange2f33ae2015-01-04 15:30:58 +0800348#ifdef CONFIG_LPUART
Alison Wange2f33ae2015-01-04 15:30:58 +0800349#define CONFIG_LPUART_32B_REG
350#else
Wang Huanf0ce7d62014-09-05 13:52:44 +0800351#define CONFIG_CONS_INDEX 1
Wang Huanf0ce7d62014-09-05 13:52:44 +0800352#define CONFIG_SYS_NS16550_SERIAL
York Sun89381742016-02-08 13:04:17 -0800353#ifndef CONFIG_DM_SERIAL
Wang Huanf0ce7d62014-09-05 13:52:44 +0800354#define CONFIG_SYS_NS16550_REG_SIZE 1
York Sun89381742016-02-08 13:04:17 -0800355#endif
Wang Huanf0ce7d62014-09-05 13:52:44 +0800356#define CONFIG_SYS_NS16550_CLK get_serial_clock()
Alison Wange2f33ae2015-01-04 15:30:58 +0800357#endif
Wang Huanf0ce7d62014-09-05 13:52:44 +0800358
Wang Huanf0ce7d62014-09-05 13:52:44 +0800359/*
360 * I2C
361 */
Wang Huanf0ce7d62014-09-05 13:52:44 +0800362#define CONFIG_SYS_I2C
363#define CONFIG_SYS_I2C_MXC
Albert ARIBAUD \\(3ADEV\\)eb943872015-09-21 22:43:38 +0200364#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
365#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
York Sunf1a52162015-03-20 10:20:40 -0700366#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
Wang Huanf0ce7d62014-09-05 13:52:44 +0800367
368/*
369 * I2C bus multiplexer
370 */
371#define I2C_MUX_PCA_ADDR_PRI 0x77
372#define I2C_MUX_CH_DEFAULT 0x8
Xiubo Li27e2fe62014-12-16 14:50:33 +0800373#define I2C_MUX_CH_CH7301 0xC
Wang Huanf0ce7d62014-09-05 13:52:44 +0800374
375/*
376 * MMC
377 */
Wang Huanf0ce7d62014-09-05 13:52:44 +0800378#define CONFIG_FSL_ESDHC
Wang Huanf0ce7d62014-09-05 13:52:44 +0800379
Haikun Wangb134e592015-06-29 13:08:46 +0530380/* SPI */
Alison Wang34de5e42016-02-02 15:16:23 +0800381#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
Haikun Wangb134e592015-06-29 13:08:46 +0530382/* QSPI */
Alison Wang2145a372014-12-09 17:38:02 +0800383#define QSPI0_AMBA_BASE 0x40000000
384#define FSL_QSPI_FLASH_SIZE (1 << 24)
385#define FSL_QSPI_FLASH_NUM 2
386
Haikun Wangb134e592015-06-29 13:08:46 +0530387/* DSPI */
Haikun Wangb134e592015-06-29 13:08:46 +0530388
389/* DM SPI */
390#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
Haikun Wangb134e592015-06-29 13:08:46 +0530391#define CONFIG_DM_SPI_FLASH
Jagan Teki79ec07c2015-06-27 22:04:55 +0530392#define CONFIG_SPI_FLASH_DATAFLASH
Haikun Wangb134e592015-06-29 13:08:46 +0530393#endif
Alison Wang2145a372014-12-09 17:38:02 +0800394#endif
395
Wang Huanf0ce7d62014-09-05 13:52:44 +0800396/*
Nikhil Badola4da7bae52014-10-17 11:37:25 +0530397 * USB
398 */
Ramneek Mehresh757219e2015-05-29 14:47:22 +0530399/* EHCI Support - disbaled by default */
400/*#define CONFIG_HAS_FSL_DR_USB*/
Nikhil Badola4da7bae52014-10-17 11:37:25 +0530401
402#ifdef CONFIG_HAS_FSL_DR_USB
Ramneek Mehresh757219e2015-05-29 14:47:22 +0530403#define CONFIG_USB_EHCI_FSL
404#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
405#endif
Nikhil Badola4da7bae52014-10-17 11:37:25 +0530406
Nikhil Badola4da7bae52014-10-17 11:37:25 +0530407/*
Xiubo Li27e2fe62014-12-16 14:50:33 +0800408 * Video
409 */
Sanchayan Maitye15479b2017-04-11 11:12:09 +0530410#ifdef CONFIG_VIDEO_FSL_DCU_FB
Xiubo Li27e2fe62014-12-16 14:50:33 +0800411#define CONFIG_VIDEO_LOGO
412#define CONFIG_VIDEO_BMP_LOGO
413
414#define CONFIG_FSL_DIU_CH7301
415#define CONFIG_SYS_I2C_DVI_BUS_NUM 0
416#define CONFIG_SYS_I2C_QIXIS_ADDR 0x66
417#define CONFIG_SYS_I2C_DVI_ADDR 0x75
418#endif
419
420/*
Wang Huanf0ce7d62014-09-05 13:52:44 +0800421 * eTSEC
422 */
423#define CONFIG_TSEC_ENET
424
425#ifdef CONFIG_TSEC_ENET
426#define CONFIG_MII
427#define CONFIG_MII_DEFAULT_TSEC 3
428#define CONFIG_TSEC1 1
429#define CONFIG_TSEC1_NAME "eTSEC1"
430#define CONFIG_TSEC2 1
431#define CONFIG_TSEC2_NAME "eTSEC2"
432#define CONFIG_TSEC3 1
433#define CONFIG_TSEC3_NAME "eTSEC3"
434
435#define TSEC1_PHY_ADDR 1
436#define TSEC2_PHY_ADDR 2
437#define TSEC3_PHY_ADDR 3
438
439#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
440#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
441#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
442
443#define TSEC1_PHYIDX 0
444#define TSEC2_PHYIDX 0
445#define TSEC3_PHYIDX 0
446
447#define CONFIG_ETHPRIME "eTSEC1"
448
Wang Huanf0ce7d62014-09-05 13:52:44 +0800449#define CONFIG_PHY_REALTEK
450
451#define CONFIG_HAS_ETH0
452#define CONFIG_HAS_ETH1
453#define CONFIG_HAS_ETH2
454
455#define CONFIG_FSL_SGMII_RISER 1
456#define SGMII_RISER_PHY_OFFSET 0x1b
457
458#ifdef CONFIG_FSL_SGMII_RISER
459#define CONFIG_SYS_TBIPA_VALUE 8
460#endif
461
462#endif
Minghuan Liana4d6b612014-10-31 13:43:44 +0800463
464/* PCIe */
Robert P. J. Daya8099812016-05-03 19:52:49 -0400465#define CONFIG_PCIE1 /* PCIE controller 1 */
466#define CONFIG_PCIE2 /* PCIE controller 2 */
Minghuan Liana4d6b612014-10-31 13:43:44 +0800467
Minghuan Lian0c1593a2015-01-21 17:29:19 +0800468#ifdef CONFIG_PCI
Minghuan Lian0c1593a2015-01-21 17:29:19 +0800469#define CONFIG_PCI_SCAN_SHOW
Minghuan Lian0c1593a2015-01-21 17:29:19 +0800470#endif
471
Wang Huanf0ce7d62014-09-05 13:52:44 +0800472#define CONFIG_CMDLINE_TAG
473#define CONFIG_CMDLINE_EDITING
Alison Wang9da51782014-12-03 15:00:47 +0800474
Xiubo Li563e3ce2014-11-21 17:40:57 +0800475#define CONFIG_PEN_ADDR_BIG_ENDIAN
Mingkai Hu5b0df8a2015-10-26 19:47:41 +0800476#define CONFIG_LAYERSCAPE_NS_ACCESS
Xiubo Li563e3ce2014-11-21 17:40:57 +0800477#define CONFIG_SMP_PEN_ADDR 0x01ee0200
Andre Przywara70c78932017-02-16 01:20:19 +0000478#define COUNTER_FREQUENCY 12500000
Xiubo Li563e3ce2014-11-21 17:40:57 +0800479
Wang Huanf0ce7d62014-09-05 13:52:44 +0800480#define CONFIG_HWCONFIG
Zhuoyu Zhangfe4f2882015-08-17 18:55:12 +0800481#define HWCONFIG_BUFFER_SIZE 256
482
483#define CONFIG_FSL_DEVICE_DISABLE
Wang Huanf0ce7d62014-09-05 13:52:44 +0800484
Wang Huanf0ce7d62014-09-05 13:52:44 +0800485
Alison Wang27666082017-05-16 10:45:57 +0800486#define CONFIG_SYS_QE_FW_ADDR 0x60940000
Zhao Qiang9fc2f302014-09-26 16:25:32 +0800487
Alison Wange2f33ae2015-01-04 15:30:58 +0800488#ifdef CONFIG_LPUART
489#define CONFIG_EXTRA_ENV_SETTINGS \
490 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
Alison Wangf6370242015-11-05 11:16:26 +0800491 "fdt_high=0xffffffff\0" \
492 "initrd_high=0xffffffff\0" \
Alison Wange2f33ae2015-01-04 15:30:58 +0800493 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
494#else
Wang Huanf0ce7d62014-09-05 13:52:44 +0800495#define CONFIG_EXTRA_ENV_SETTINGS \
496 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
Alison Wangf6370242015-11-05 11:16:26 +0800497 "fdt_high=0xffffffff\0" \
498 "initrd_high=0xffffffff\0" \
Wang Huanf0ce7d62014-09-05 13:52:44 +0800499 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
Alison Wange2f33ae2015-01-04 15:30:58 +0800500#endif
Wang Huanf0ce7d62014-09-05 13:52:44 +0800501
502/*
503 * Miscellaneous configurable options
504 */
505#define CONFIG_SYS_LONGHELP /* undef to save memory */
Wang Huanf0ce7d62014-09-05 13:52:44 +0800506#define CONFIG_AUTO_COMPLETE
Wang Huanf0ce7d62014-09-05 13:52:44 +0800507
Wang Huanf0ce7d62014-09-05 13:52:44 +0800508#define CONFIG_SYS_MEMTEST_START 0x80000000
509#define CONFIG_SYS_MEMTEST_END 0x9fffffff
510
511#define CONFIG_SYS_LOAD_ADDR 0x82000000
Wang Huanf0ce7d62014-09-05 13:52:44 +0800512
Xiubo Li03d40aa2014-11-21 17:40:59 +0800513#define CONFIG_LS102XA_STREAM_ID
514
Wang Huanf0ce7d62014-09-05 13:52:44 +0800515#define CONFIG_SYS_INIT_SP_OFFSET \
516 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
517#define CONFIG_SYS_INIT_SP_ADDR \
518 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
519
Alison Wang9da51782014-12-03 15:00:47 +0800520#ifdef CONFIG_SPL_BUILD
521#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
522#else
Wang Huanf0ce7d62014-09-05 13:52:44 +0800523#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Alison Wang9da51782014-12-03 15:00:47 +0800524#endif
Wang Huanf0ce7d62014-09-05 13:52:44 +0800525
526/*
527 * Environment
528 */
529#define CONFIG_ENV_OVERWRITE
530
Alison Wang9da51782014-12-03 15:00:47 +0800531#if defined(CONFIG_SD_BOOT)
Alison Wang27666082017-05-16 10:45:57 +0800532#define CONFIG_ENV_OFFSET 0x300000
Alison Wang9da51782014-12-03 15:00:47 +0800533#define CONFIG_SYS_MMC_ENV_DEV 0
534#define CONFIG_ENV_SIZE 0x2000
Alison Wang2145a372014-12-09 17:38:02 +0800535#elif defined(CONFIG_QSPI_BOOT)
Alison Wang2145a372014-12-09 17:38:02 +0800536#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
Alison Wang27666082017-05-16 10:45:57 +0800537#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
Alison Wang2145a372014-12-09 17:38:02 +0800538#define CONFIG_ENV_SECT_SIZE 0x10000
Alison Wangab98bb52014-12-09 17:38:14 +0800539#elif defined(CONFIG_NAND_BOOT)
Alison Wangab98bb52014-12-09 17:38:14 +0800540#define CONFIG_ENV_SIZE 0x2000
541#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
Alison Wang9da51782014-12-03 15:00:47 +0800542#else
Alison Wang27666082017-05-16 10:45:57 +0800543#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
Wang Huanf0ce7d62014-09-05 13:52:44 +0800544#define CONFIG_ENV_SIZE 0x2000
545#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
Alison Wang9da51782014-12-03 15:00:47 +0800546#endif
Wang Huanf0ce7d62014-09-05 13:52:44 +0800547
Ruchika Gupta901ae762014-10-15 11:39:06 +0530548#define CONFIG_MISC_INIT_R
549
Aneesh Bansal962021a2016-01-22 16:37:22 +0530550#include <asm/fsl_secure_boot.h>
Alison Wang13b0bb82016-01-15 15:29:32 +0800551#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Ruchika Gupta901ae762014-10-15 11:39:06 +0530552
Wang Huanf0ce7d62014-09-05 13:52:44 +0800553#endif