arch/arm/dts/sam9x60.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * sam9x60.dtsi - Device Tree Include file for SAM9X60 SoC.
 *
 * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
 *
 * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
 */

#include "skeleton.dtsi"
#include <dt-bindings/dma/at91.h>
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clk/at91.h>

/{
	model = "Microchip SAM9X60 SoC";
	compatible = "microchip,sam9x60";

	aliases {
		serial0 = &dbgu;
		gpio0 = &pioA;
		gpio1 = &pioB;
		gpio2 = &pioC;
		gpio3 = &pioD;
		spi0 = &qspi;
	};

	clocks {
		slow_rc_osc: slow_rc_osc {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <18500>;
		};

		main_rc: main_rc {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <12000000>;
		};

		slow_xtal: slow_xtal {
			compatible = "fixed-clock";
			#clock-cells = <0>;
		};

		main_xtal: main_xtal {
			compatible = "fixed-clock";
			#clock-cells = <0>;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		ARM9260_0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,arm926ej-s";
			clocks = <&pmc PMC_TYPE_CORE 19>, <&pmc PMC_TYPE_CORE 11>, <&main_xtal>;
			clock-names = "cpu", "master", "xtal";
		};
	};

	ahb {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		sdhci0: sdhci-host@80000000 {
			compatible = "microchip,sam9x60-sdhci";
			reg = <0x80000000 0x300>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>;
			clock-names = "hclock", "multclk";
			assigned-clocks = <&pmc PMC_TYPE_GCK 12>;
			assigned-clock-rates = <100000000>;
			assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* ID_PLL_A_DIV */
			bus-width = <4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_sdhci0>;
		};

		apb {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			qspi: spi@f0014000 {
				compatible = "microchip,sam9x60-qspi";
				reg = <0xf0014000 0x100>, <0x70000000 0x10000000>;
				reg-names = "qspi_base", "qspi_mmap";
				clocks =  <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_SYSTEM 18>; /* ID_QSPI */
				clock-names = "pclk", "qspick";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			flx0: flexcom@f801c600 {
				compatible = "atmel,sama5d2-flexcom";
				reg = <0xf801c000 0x200>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0xf801c000 0x800>;
				status = "disabled";
			};

			macb0: ethernet@f802c000 {
				compatible = "cdns,sam9x60-macb", "cdns,macb";
				reg = <0xf802c000 0x100>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_macb0_rmii>;
				clock-names = "hclk", "pclk";
				clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>;
				status = "disabled";
			};

			dbgu: serial@fffff200 {
				compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
				reg = <0xfffff200 0x200>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_dbgu>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
				clock-names = "usart";
			};

			pinctrl {
				#address-cells = <1>;
				#size-cells = <1>;
				compatible = "microchip,sam9x60-pinctrl", "simple-bus";
				ranges = <0xfffff400 0xfffff400 0x800>;
				reg = <0xfffff400 0x200		/* pioA */
				       0xfffff600 0x200		/* pioB */
				       0xfffff800 0x200		/* pioC */
				       0xfffffa00 0x200>;	/* pioD */

				/* shared pinctrl settings */
				dbgu {
					pinctrl_dbgu: dbgu-0 {
						atmel,pins =
							<AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
							AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};
				};

				macb0 {
					pinctrl_macb0_rmii: macb0_rmii-0 {
						atmel,pins =
							<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB0 periph A */
							 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB1 periph A */
							 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB2 periph A */
							 AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB3 periph A */
							 AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB4 periph A */
							 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB5 periph A */
							 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB6 periph A */
							 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB7 periph A */
							 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB9 periph A */
							 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB10 periph A */
					};
				};

				sdhci0 {
					pinctrl_sdhci0: sdhci0 {
						atmel,pins =
							<AT91_PIOA 17 AT91_PERIPH_A
							 (AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)	/* PA17 CK  periph A with pullup */
							 AT91_PIOA 16 AT91_PERIPH_A
							 (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)	/* PA16 CMD periph A with pullup */
							 AT91_PIOA 15 AT91_PERIPH_A
							 (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)	/* PA15 DAT0 periph A */
							 AT91_PIOA 18 AT91_PERIPH_A
							 (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)	/* PA18 DAT1 periph A with pullup */
							 AT91_PIOA 19 AT91_PERIPH_A
							 (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)	/* PA19 DAT2 periph A with pullup */
							 AT91_PIOA 20 AT91_PERIPH_A
							 (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>;	/* PA20 DAT3 periph A with pullup */
					};
				};
			};

			pioA: gpio@fffff400 {
				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
				reg = <0xfffff400 0x200>;
				#gpio-cells = <2>;
				gpio-controller;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
			};

			pioB: gpio@fffff600 {
				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
				reg = <0xfffff600 0x200>;
				#gpio-cells = <2>;
				gpio-controller;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
			};

			pioC: gpio@fffff800 {
				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
				reg = <0xfffff800 0x200>;
				#gpio-cells = <2>;
				gpio-controller;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
			};

			pioD: gpio@fffffa00 {
				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
				reg = <0xfffffa00 0x200>;
				#gpio-cells = <2>;
				gpio-controller;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
			};

			pmc: pmc@fffffc00 {
				compatible = "microchip,sam9x60-pmc";
				reg = <0xfffffc00 0x200>;
				#clock-cells = <2>;
				clocks = <&clk32 1>, <&clk32 0>, <&main_xtal>, <&main_rc>;
				clock-names = "td_slck", "md_slck", "main_xtal", "main_rc";
				status = "okay";
			};

			reset_controller: rstc@fffffe00 {
				compatible = "microchip,sam9x60-rstc";
				reg = <0xfffffe00 0x10>;
				clocks = <&clk32 0>;
			};

			pit: timer@fffffe40 {
				compatible = "atmel,at91sam9260-pit";
				reg = <0xfffffe40 0x10>;
				clocks = <&pmc PMC_TYPE_CORE 11>; /* ID_MCK. */
			};

			pit64b0: timer@f0028000 {
				compatible = "microchip,sam9x60-pit64b";
				reg = <0xf0028000 0xec>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>;
				clock-names = "pclk", "gclk";
			};

			clk32: sckc@fffffe50 {
				compatible = "microchip,sam9x60-sckc";
				reg = <0xfffffe50 0x4>;
				clocks = <&slow_rc_osc>, <&slow_xtal>;
				#clock-cells = <1>;
			};
		};
	};

	onewire_tm: onewire {
		compatible = "w1-gpio";
		status = "disabled";
	};
};