| Sumit Garg | 89a8ec9 | 2022-07-12 12:42:12 +0530 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Qualcomm QCS404 based evaluation board device tree source |
| 4 | * |
| 5 | * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org> |
| 6 | */ |
| 7 | |
| 8 | /dts-v1/; |
| 9 | |
| 10 | #include "skeleton64.dtsi" |
| 11 | #include <dt-bindings/gpio/gpio.h> |
| 12 | #include <dt-bindings/pinctrl/pinctrl-snapdragon.h> |
| 13 | #include <dt-bindings/clock/qcom,gcc-qcs404.h> |
| 14 | |
| 15 | / { |
| 16 | model = "Qualcomm Technologies, Inc. QCS404 EVB"; |
| 17 | compatible = "qcom,qcs404-evb", "qcom,qcs404"; |
| 18 | #address-cells = <0x2>; |
| 19 | #size-cells = <0x2>; |
| 20 | |
| 21 | chosen { |
| 22 | stdout-path = "serial0:115200n8"; |
| 23 | }; |
| 24 | |
| 25 | aliases { |
| 26 | serial0 = &debug_uart; |
| 27 | }; |
| 28 | |
| 29 | memory { |
| 30 | device_type = "memory"; |
| 31 | reg = <0 0x80000000 0 0x40000000>; |
| 32 | }; |
| 33 | |
| 34 | soc { |
| 35 | #address-cells = <0x1>; |
| 36 | #size-cells = <0x1>; |
| 37 | ranges = <0x0 0x0 0x0 0xffffffff>; |
| 38 | compatible = "simple-bus"; |
| 39 | |
| 40 | pinctrl_north@1300000 { |
| 41 | compatible = "qcom,tlmm-qcs404"; |
| 42 | reg = <0x1300000 0x200000>; |
| 43 | |
| 44 | blsp1_uart2: uart { |
| 45 | pins = "GPIO_17", "GPIO_18"; |
| 46 | function = "blsp_uart2"; |
| 47 | }; |
| 48 | }; |
| 49 | |
| 50 | gcc: clock-controller@1800000 { |
| 51 | compatible = "qcom,gcc-qcs404"; |
| 52 | reg = <0x1800000 0x80000>; |
| 53 | #address-cells = <0x1>; |
| 54 | #size-cells = <0x0>; |
| 55 | }; |
| 56 | |
| 57 | debug_uart: serial@78b1000 { |
| 58 | compatible = "qcom,msm-uartdm-v1.4"; |
| 59 | reg = <0x78b1000 0x200>; |
| 60 | clock = <&gcc GCC_BLSP1_UART2_APPS_CLK>, |
| 61 | <&gcc GCC_BLSP1_AHB_CLK>; |
| 62 | bit-rate = <0xFF>; |
| 63 | pinctrl-names = "uart"; |
| 64 | pinctrl-0 = <&blsp1_uart2>; |
| 65 | }; |
| 66 | |
| 67 | sdhci@7804000 { |
| 68 | compatible = "qcom,sdhci-msm-v5"; |
| 69 | reg = <0x7804000 0x1000 0x7805000 0x1000>; |
| 70 | clock = <&gcc GCC_SDCC1_APPS_CLK>, |
| 71 | <&gcc GCC_SDCC1_AHB_CLK>; |
| 72 | bus-width = <0x8>; |
| 73 | index = <0x0>; |
| 74 | non-removable; |
| 75 | mmc-ddr-1_8v; |
| 76 | mmc-hs400-1_8v; |
| 77 | }; |
| 78 | }; |
| 79 | }; |
| 80 | |
| 81 | #include "qcs404-evb-uboot.dtsi" |