Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Sedji Gaouaou | 538566d | 2009-07-09 10:16:29 +0200 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2007-2008 |
Stelian Pop | 5ee0c7f | 2011-11-01 00:00:39 +0100 | [diff] [blame] | 4 | * Stelian Pop <stelian@popies.net> |
Sedji Gaouaou | 538566d | 2009-07-09 10:16:29 +0200 | [diff] [blame] | 5 | * Lead Tech Design <www.leadtechdesign.com> |
Sedji Gaouaou | 538566d | 2009-07-09 10:16:29 +0200 | [diff] [blame] | 6 | */ |
| 7 | |
Tom Rini | 5f201cd | 2024-04-30 20:41:08 -0600 | [diff] [blame] | 8 | #include <config.h> |
Wenyou Yang | cf6667c | 2017-04-18 15:15:50 +0800 | [diff] [blame] | 9 | #include <debug_uart.h> |
Simon Glass | 8e16b1e | 2019-12-28 10:45:05 -0700 | [diff] [blame] | 10 | #include <init.h> |
Simon Glass | 0c36441 | 2019-12-28 10:44:48 -0700 | [diff] [blame] | 11 | #include <net.h> |
Simon Glass | f5c208d | 2019-11-14 12:57:20 -0700 | [diff] [blame] | 12 | #include <vsprintf.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 13 | #include <asm/global_data.h> |
Thomas Petazzoni | a5e8576 | 2011-08-04 11:08:50 +0000 | [diff] [blame] | 14 | #include <asm/io.h> |
Bo Shen | c56e9f4 | 2015-03-27 14:23:34 +0800 | [diff] [blame] | 15 | #include <asm/arch/clk.h> |
Thomas Petazzoni | a5e8576 | 2011-08-04 11:08:50 +0000 | [diff] [blame] | 16 | #include <asm/arch/at91sam9g45_matrix.h> |
Sedji Gaouaou | 538566d | 2009-07-09 10:16:29 +0200 | [diff] [blame] | 17 | #include <asm/arch/at91sam9_smc.h> |
| 18 | #include <asm/arch/at91_common.h> |
Sedji Gaouaou | 538566d | 2009-07-09 10:16:29 +0200 | [diff] [blame] | 19 | #include <asm/arch/gpio.h> |
Thomas Petazzoni | a5e8576 | 2011-08-04 11:08:50 +0000 | [diff] [blame] | 20 | #include <asm/arch/clk.h> |
Masahiro Yamada | 2b7a873 | 2017-11-30 13:45:24 +0900 | [diff] [blame] | 21 | #include <linux/mtd/rawnand.h> |
Sedji Gaouaou | 538566d | 2009-07-09 10:16:29 +0200 | [diff] [blame] | 22 | #include <atmel_lcdc.h> |
Simon Glass | 0ffb9d6 | 2017-05-31 19:47:48 -0600 | [diff] [blame] | 23 | #include <asm/mach-types.h> |
Sedji Gaouaou | 538566d | 2009-07-09 10:16:29 +0200 | [diff] [blame] | 24 | |
| 25 | DECLARE_GLOBAL_DATA_PTR; |
| 26 | |
| 27 | /* ------------------------------------------------------------------------- */ |
| 28 | /* |
| 29 | * Miscelaneous platform dependent initialisations |
| 30 | */ |
| 31 | |
| 32 | #ifdef CONFIG_CMD_NAND |
Thomas Petazzoni | a5e8576 | 2011-08-04 11:08:50 +0000 | [diff] [blame] | 33 | void at91sam9m10g45ek_nand_hw_init(void) |
Sedji Gaouaou | 538566d | 2009-07-09 10:16:29 +0200 | [diff] [blame] | 34 | { |
Thomas Petazzoni | a5e8576 | 2011-08-04 11:08:50 +0000 | [diff] [blame] | 35 | struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; |
| 36 | struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; |
Sedji Gaouaou | 538566d | 2009-07-09 10:16:29 +0200 | [diff] [blame] | 37 | unsigned long csa; |
| 38 | |
| 39 | /* Enable CS3 */ |
Thomas Petazzoni | a5e8576 | 2011-08-04 11:08:50 +0000 | [diff] [blame] | 40 | csa = readl(&matrix->ebicsa); |
| 41 | csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; |
| 42 | writel(csa, &matrix->ebicsa); |
Sedji Gaouaou | 538566d | 2009-07-09 10:16:29 +0200 | [diff] [blame] | 43 | |
| 44 | /* Configure SMC CS3 for NAND/SmartMedia */ |
Thomas Petazzoni | a5e8576 | 2011-08-04 11:08:50 +0000 | [diff] [blame] | 45 | writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | |
| 46 | AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), |
| 47 | &smc->cs[3].setup); |
| 48 | writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) | |
| 49 | AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2), |
| 50 | &smc->cs[3].pulse); |
| 51 | writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4), |
| 52 | &smc->cs[3].cycle); |
| 53 | writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | |
| 54 | AT91_SMC_MODE_EXNW_DISABLE | |
Sedji Gaouaou | 538566d | 2009-07-09 10:16:29 +0200 | [diff] [blame] | 55 | #ifdef CONFIG_SYS_NAND_DBW_16 |
Thomas Petazzoni | a5e8576 | 2011-08-04 11:08:50 +0000 | [diff] [blame] | 56 | AT91_SMC_MODE_DBW_16 | |
Sedji Gaouaou | 538566d | 2009-07-09 10:16:29 +0200 | [diff] [blame] | 57 | #else /* CONFIG_SYS_NAND_DBW_8 */ |
Thomas Petazzoni | a5e8576 | 2011-08-04 11:08:50 +0000 | [diff] [blame] | 58 | AT91_SMC_MODE_DBW_8 | |
Sedji Gaouaou | 538566d | 2009-07-09 10:16:29 +0200 | [diff] [blame] | 59 | #endif |
Thomas Petazzoni | a5e8576 | 2011-08-04 11:08:50 +0000 | [diff] [blame] | 60 | AT91_SMC_MODE_TDF_CYCLE(3), |
| 61 | &smc->cs[3].mode); |
Sedji Gaouaou | 538566d | 2009-07-09 10:16:29 +0200 | [diff] [blame] | 62 | |
Wenyou Yang | 78f8976 | 2016-02-03 10:16:50 +0800 | [diff] [blame] | 63 | at91_periph_clk_enable(ATMEL_ID_PIOC); |
Sedji Gaouaou | 538566d | 2009-07-09 10:16:29 +0200 | [diff] [blame] | 64 | |
| 65 | /* Configure RDY/BSY */ |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 66 | at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1); |
Sedji Gaouaou | 538566d | 2009-07-09 10:16:29 +0200 | [diff] [blame] | 67 | |
| 68 | /* Enable NandFlash */ |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 69 | at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1); |
Sedji Gaouaou | 538566d | 2009-07-09 10:16:29 +0200 | [diff] [blame] | 70 | } |
| 71 | #endif |
| 72 | |
Bo Shen | c56e9f4 | 2015-03-27 14:23:34 +0800 | [diff] [blame] | 73 | #if defined(CONFIG_SPL_BUILD) |
| 74 | #include <spl.h> |
| 75 | #include <nand.h> |
| 76 | |
| 77 | void at91_spl_board_init(void) |
| 78 | { |
| 79 | /* |
| 80 | * On the at91sam9m10g45ek board, the chip wm9711 stays in the |
| 81 | * test mode, so it needs do some action to exit test mode. |
| 82 | */ |
| 83 | at91_periph_clk_enable(ATMEL_ID_PIODE); |
| 84 | at91_set_gpio_output(AT91_PIN_PD7, 0); |
| 85 | at91_set_gpio_output(AT91_PIN_PD8, 0); |
| 86 | at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1); |
| 87 | at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1); |
| 88 | |
Wenyou Yang | e035ea7 | 2017-09-14 11:07:44 +0800 | [diff] [blame] | 89 | #ifdef CONFIG_SD_BOOT |
Bo Shen | c56e9f4 | 2015-03-27 14:23:34 +0800 | [diff] [blame] | 90 | at91_mci_hw_init(); |
Wenyou Yang | e035ea7 | 2017-09-14 11:07:44 +0800 | [diff] [blame] | 91 | #elif CONFIG_NAND_BOOT |
Bo Shen | c56e9f4 | 2015-03-27 14:23:34 +0800 | [diff] [blame] | 92 | at91sam9m10g45ek_nand_hw_init(); |
| 93 | #endif |
| 94 | } |
| 95 | |
| 96 | #include <asm/arch/atmel_mpddrc.h> |
Wenyou Yang | aa0a58d | 2016-02-01 18:12:15 +0800 | [diff] [blame] | 97 | static void ddr2_conf(struct atmel_mpddrc_config *ddr2) |
Bo Shen | c56e9f4 | 2015-03-27 14:23:34 +0800 | [diff] [blame] | 98 | { |
| 99 | ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); |
| 100 | |
| 101 | ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | |
| 102 | ATMEL_MPDDRC_CR_NR_ROW_14 | |
| 103 | ATMEL_MPDDRC_CR_DQMS_SHARED | |
| 104 | ATMEL_MPDDRC_CR_CAS_DDR_CAS3); |
| 105 | |
| 106 | ddr2->rtr = 0x24b; |
| 107 | |
| 108 | ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */ |
| 109 | 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */ |
| 110 | 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */ |
| 111 | 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 60 ns */ |
| 112 | 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */ |
| 113 | 1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/ |
| 114 | 1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */ |
| 115 | 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */ |
| 116 | |
| 117 | ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */ |
| 118 | 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | |
| 119 | 16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | |
| 120 | 14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); |
| 121 | |
| 122 | ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | |
| 123 | 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | |
| 124 | 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | |
| 125 | 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); |
| 126 | } |
| 127 | |
| 128 | void mem_init(void) |
| 129 | { |
Wenyou Yang | aa0a58d | 2016-02-01 18:12:15 +0800 | [diff] [blame] | 130 | struct atmel_mpddrc_config ddr2; |
Bo Shen | c56e9f4 | 2015-03-27 14:23:34 +0800 | [diff] [blame] | 131 | |
| 132 | ddr2_conf(&ddr2); |
| 133 | |
Wenyou Yang | 78f8976 | 2016-02-03 10:16:50 +0800 | [diff] [blame] | 134 | at91_system_clk_enable(AT91_PMC_DDR); |
Bo Shen | c56e9f4 | 2015-03-27 14:23:34 +0800 | [diff] [blame] | 135 | |
Bo Shen | c56e9f4 | 2015-03-27 14:23:34 +0800 | [diff] [blame] | 136 | /* DDRAM2 Controller initialize */ |
Erik van Luijk | 59d780a | 2015-08-13 15:43:18 +0200 | [diff] [blame] | 137 | ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2); |
Bo Shen | c56e9f4 | 2015-03-27 14:23:34 +0800 | [diff] [blame] | 138 | } |
| 139 | #endif |
| 140 | |
Sergey Matyukevich | d25010d | 2010-06-09 23:09:06 +0400 | [diff] [blame] | 141 | #ifdef CONFIG_CMD_USB |
| 142 | static void at91sam9m10g45ek_usb_hw_init(void) |
| 143 | { |
Wenyou Yang | 78f8976 | 2016-02-03 10:16:50 +0800 | [diff] [blame] | 144 | at91_periph_clk_enable(ATMEL_ID_PIODE); |
Sergey Matyukevich | d25010d | 2010-06-09 23:09:06 +0400 | [diff] [blame] | 145 | |
| 146 | at91_set_gpio_output(AT91_PIN_PD1, 0); |
| 147 | at91_set_gpio_output(AT91_PIN_PD3, 0); |
| 148 | } |
| 149 | #endif |
| 150 | |
Wenyou Yang | cf6667c | 2017-04-18 15:15:50 +0800 | [diff] [blame] | 151 | #ifdef CONFIG_DEBUG_UART_BOARD_INIT |
| 152 | void board_debug_uart_init(void) |
| 153 | { |
| 154 | at91_seriald_hw_init(); |
| 155 | } |
| 156 | #endif |
| 157 | |
| 158 | #ifdef CONFIG_BOARD_EARLY_INIT_F |
Thomas Petazzoni | a5e8576 | 2011-08-04 11:08:50 +0000 | [diff] [blame] | 159 | int board_early_init_f(void) |
| 160 | { |
Thomas Petazzoni | a5e8576 | 2011-08-04 11:08:50 +0000 | [diff] [blame] | 161 | return 0; |
| 162 | } |
Wenyou Yang | cf6667c | 2017-04-18 15:15:50 +0800 | [diff] [blame] | 163 | #endif |
Thomas Petazzoni | a5e8576 | 2011-08-04 11:08:50 +0000 | [diff] [blame] | 164 | |
Sedji Gaouaou | 538566d | 2009-07-09 10:16:29 +0200 | [diff] [blame] | 165 | int board_init(void) |
| 166 | { |
Sedji Gaouaou | 538566d | 2009-07-09 10:16:29 +0200 | [diff] [blame] | 167 | /* arch number of AT91SAM9M10G45EK-Board */ |
Sedji Gaouaou | 538566d | 2009-07-09 10:16:29 +0200 | [diff] [blame] | 168 | gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK; |
Thomas Petazzoni | a5e8576 | 2011-08-04 11:08:50 +0000 | [diff] [blame] | 169 | |
Sedji Gaouaou | 538566d | 2009-07-09 10:16:29 +0200 | [diff] [blame] | 170 | /* adress of boot parameters */ |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 171 | gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; |
Sedji Gaouaou | 538566d | 2009-07-09 10:16:29 +0200 | [diff] [blame] | 172 | |
Sedji Gaouaou | 538566d | 2009-07-09 10:16:29 +0200 | [diff] [blame] | 173 | #ifdef CONFIG_CMD_NAND |
| 174 | at91sam9m10g45ek_nand_hw_init(); |
| 175 | #endif |
Sergey Matyukevich | d25010d | 2010-06-09 23:09:06 +0400 | [diff] [blame] | 176 | #ifdef CONFIG_CMD_USB |
| 177 | at91sam9m10g45ek_usb_hw_init(); |
| 178 | #endif |
Sedji Gaouaou | 538566d | 2009-07-09 10:16:29 +0200 | [diff] [blame] | 179 | return 0; |
| 180 | } |
| 181 | |
| 182 | int dram_init(void) |
| 183 | { |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 184 | gd->ram_size = get_ram_size((void *) CFG_SYS_SDRAM_BASE, |
| 185 | CFG_SYS_SDRAM_SIZE); |
Sedji Gaouaou | 538566d | 2009-07-09 10:16:29 +0200 | [diff] [blame] | 186 | return 0; |
| 187 | } |
| 188 | |
| 189 | #ifdef CONFIG_RESET_PHY_R |
| 190 | void reset_phy(void) |
| 191 | { |
Sedji Gaouaou | 538566d | 2009-07-09 10:16:29 +0200 | [diff] [blame] | 192 | } |
| 193 | #endif |