Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Donghwa Lee | 0955271 | 2012-04-05 19:36:10 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2012 Samsung Electronics |
| 4 | * Donghwa Lee <dh09.lee@samsung.com> |
Donghwa Lee | 0955271 | 2012-04-05 19:36:10 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
Tom Rini | 525a68e | 2024-04-30 07:35:52 -0600 | [diff] [blame] | 7 | #include <config.h> |
Donghwa Lee | 0955271 | 2012-04-05 19:36:10 +0000 | [diff] [blame] | 8 | #include <asm/io.h> |
| 9 | #include <asm/arch/system.h> |
| 10 | |
Rajeshwari Shinde | 8444807 | 2012-05-14 05:52:02 +0000 | [diff] [blame] | 11 | static void exynos5_set_usbhost_mode(unsigned int mode) |
| 12 | { |
| 13 | struct exynos5_sysreg *sysreg = |
| 14 | (struct exynos5_sysreg *)samsung_get_base_sysreg(); |
Rajeshwari Shinde | 8444807 | 2012-05-14 05:52:02 +0000 | [diff] [blame] | 15 | |
| 16 | /* Setting USB20PHY_CONFIG register to USB 2.0 HOST link */ |
| 17 | if (mode == USB20_PHY_CFG_HOST_LINK_EN) { |
| 18 | setbits_le32(&sysreg->usb20phy_cfg, |
| 19 | USB20_PHY_CFG_HOST_LINK_EN); |
| 20 | } else { |
| 21 | clrbits_le32(&sysreg->usb20phy_cfg, |
| 22 | USB20_PHY_CFG_HOST_LINK_EN); |
| 23 | } |
| 24 | } |
| 25 | |
| 26 | void set_usbhost_mode(unsigned int mode) |
| 27 | { |
| 28 | if (cpu_is_exynos5()) |
| 29 | exynos5_set_usbhost_mode(mode); |
| 30 | } |
| 31 | |
Donghwa Lee | 0955271 | 2012-04-05 19:36:10 +0000 | [diff] [blame] | 32 | static void exynos4_set_system_display(void) |
| 33 | { |
| 34 | struct exynos4_sysreg *sysreg = |
| 35 | (struct exynos4_sysreg *)samsung_get_base_sysreg(); |
| 36 | unsigned int cfg = 0; |
| 37 | |
| 38 | /* |
| 39 | * system register path set |
| 40 | * 0: MIE/MDNIE |
| 41 | * 1: FIMD Bypass |
| 42 | */ |
| 43 | cfg = readl(&sysreg->display_ctrl); |
| 44 | cfg |= (1 << 1); |
| 45 | writel(cfg, &sysreg->display_ctrl); |
| 46 | } |
| 47 | |
Donghwa Lee | bac7528 | 2012-07-02 01:15:53 +0000 | [diff] [blame] | 48 | static void exynos5_set_system_display(void) |
| 49 | { |
| 50 | struct exynos5_sysreg *sysreg = |
| 51 | (struct exynos5_sysreg *)samsung_get_base_sysreg(); |
| 52 | unsigned int cfg = 0; |
| 53 | |
| 54 | /* |
| 55 | * system register path set |
| 56 | * 0: MIE/MDNIE |
| 57 | * 1: FIMD Bypass |
| 58 | */ |
| 59 | cfg = readl(&sysreg->disp1blk_cfg); |
| 60 | cfg |= (1 << 15); |
| 61 | writel(cfg, &sysreg->disp1blk_cfg); |
| 62 | } |
| 63 | |
Donghwa Lee | 0955271 | 2012-04-05 19:36:10 +0000 | [diff] [blame] | 64 | void set_system_display_ctrl(void) |
| 65 | { |
| 66 | if (cpu_is_exynos4()) |
| 67 | exynos4_set_system_display(); |
Donghwa Lee | bac7528 | 2012-07-02 01:15:53 +0000 | [diff] [blame] | 68 | else |
| 69 | exynos5_set_system_display(); |
Donghwa Lee | 0955271 | 2012-04-05 19:36:10 +0000 | [diff] [blame] | 70 | } |