Stephen Warren | 9026dfd | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2010-2014 |
| 3 | * NVIDIA Corporation <www.nvidia.com> |
| 4 | * |
| 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 6 | */ |
| 7 | |
| 8 | #ifndef _TEGRA_PINMUX_H_ |
| 9 | #define _TEGRA_PINMUX_H_ |
| 10 | |
| 11 | #include <asm/arch/tegra.h> |
| 12 | |
| 13 | /* The pullup/pulldown state of a pin group */ |
| 14 | enum pmux_pull { |
| 15 | PMUX_PULL_NORMAL = 0, |
| 16 | PMUX_PULL_DOWN, |
| 17 | PMUX_PULL_UP, |
| 18 | }; |
| 19 | |
| 20 | /* Defines whether a pin group is tristated or in normal operation */ |
| 21 | enum pmux_tristate { |
| 22 | PMUX_TRI_NORMAL = 0, |
| 23 | PMUX_TRI_TRISTATE = 1, |
| 24 | }; |
| 25 | |
Stephen Warren | 22d57fe | 2015-02-24 14:08:24 -0700 | [diff] [blame] | 26 | #ifdef TEGRA_PMX_PINS_HAVE_E_INPUT |
Stephen Warren | 9026dfd | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 27 | enum pmux_pin_io { |
| 28 | PMUX_PIN_OUTPUT = 0, |
| 29 | PMUX_PIN_INPUT = 1, |
| 30 | PMUX_PIN_NONE, |
| 31 | }; |
Stephen Warren | 22d57fe | 2015-02-24 14:08:24 -0700 | [diff] [blame] | 32 | #endif |
Stephen Warren | 9026dfd | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 33 | |
Stephen Warren | 22d57fe | 2015-02-24 14:08:24 -0700 | [diff] [blame] | 34 | #ifdef TEGRA_PMX_PINS_HAVE_LOCK |
Stephen Warren | 9026dfd | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 35 | enum pmux_pin_lock { |
| 36 | PMUX_PIN_LOCK_DEFAULT = 0, |
| 37 | PMUX_PIN_LOCK_DISABLE, |
| 38 | PMUX_PIN_LOCK_ENABLE, |
| 39 | }; |
Stephen Warren | 22d57fe | 2015-02-24 14:08:24 -0700 | [diff] [blame] | 40 | #endif |
Stephen Warren | 9026dfd | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 41 | |
Stephen Warren | 22d57fe | 2015-02-24 14:08:24 -0700 | [diff] [blame] | 42 | #ifdef TEGRA_PMX_PINS_HAVE_OD |
Stephen Warren | 9026dfd | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 43 | enum pmux_pin_od { |
| 44 | PMUX_PIN_OD_DEFAULT = 0, |
| 45 | PMUX_PIN_OD_DISABLE, |
| 46 | PMUX_PIN_OD_ENABLE, |
| 47 | }; |
Stephen Warren | 22d57fe | 2015-02-24 14:08:24 -0700 | [diff] [blame] | 48 | #endif |
Stephen Warren | 9026dfd | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 49 | |
Stephen Warren | 22d57fe | 2015-02-24 14:08:24 -0700 | [diff] [blame] | 50 | #ifdef TEGRA_PMX_PINS_HAVE_IO_RESET |
Stephen Warren | 9026dfd | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 51 | enum pmux_pin_ioreset { |
| 52 | PMUX_PIN_IO_RESET_DEFAULT = 0, |
| 53 | PMUX_PIN_IO_RESET_DISABLE, |
| 54 | PMUX_PIN_IO_RESET_ENABLE, |
| 55 | }; |
Stephen Warren | 22d57fe | 2015-02-24 14:08:24 -0700 | [diff] [blame] | 56 | #endif |
Stephen Warren | 9026dfd | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 57 | |
Stephen Warren | 22d57fe | 2015-02-24 14:08:24 -0700 | [diff] [blame] | 58 | #ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL |
Stephen Warren | 9026dfd | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 59 | enum pmux_pin_rcv_sel { |
| 60 | PMUX_PIN_RCV_SEL_DEFAULT = 0, |
| 61 | PMUX_PIN_RCV_SEL_NORMAL, |
| 62 | PMUX_PIN_RCV_SEL_HIGH, |
| 63 | }; |
Stephen Warren | 22d57fe | 2015-02-24 14:08:24 -0700 | [diff] [blame] | 64 | #endif |
Stephen Warren | 9026dfd | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 65 | |
Stephen Warren | d9f8def | 2015-02-24 14:08:30 -0700 | [diff] [blame^] | 66 | #ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV |
| 67 | enum pmux_pin_e_io_hv { |
| 68 | PMUX_PIN_E_IO_HV_DEFAULT = 0, |
| 69 | PMUX_PIN_E_IO_HV_NORMAL, |
| 70 | PMUX_PIN_E_IO_HV_HIGH, |
| 71 | }; |
| 72 | #endif |
| 73 | |
Stephen Warren | 899a5cb | 2015-02-24 14:08:26 -0700 | [diff] [blame] | 74 | #ifdef TEGRA_PMX_GRPS_HAVE_LPMD |
| 75 | /* Defines a pin group cfg's low-power mode select */ |
| 76 | enum pmux_lpmd { |
| 77 | PMUX_LPMD_X8 = 0, |
| 78 | PMUX_LPMD_X4, |
| 79 | PMUX_LPMD_X2, |
| 80 | PMUX_LPMD_X, |
| 81 | PMUX_LPMD_NONE = -1, |
| 82 | }; |
| 83 | #endif |
| 84 | |
Stephen Warren | 97f9c68 | 2015-02-24 14:08:28 -0700 | [diff] [blame] | 85 | #if defined(TEGRA_PMX_PINS_HAVE_SCHMT) || defined(TEGRA_PMX_GRPS_HAVE_SCHMT) |
Stephen Warren | 899a5cb | 2015-02-24 14:08:26 -0700 | [diff] [blame] | 86 | /* Defines whether a pin group cfg's schmidt is enabled or not */ |
| 87 | enum pmux_schmt { |
| 88 | PMUX_SCHMT_DISABLE = 0, |
| 89 | PMUX_SCHMT_ENABLE = 1, |
| 90 | PMUX_SCHMT_NONE = -1, |
| 91 | }; |
| 92 | #endif |
| 93 | |
Stephen Warren | 97f9c68 | 2015-02-24 14:08:28 -0700 | [diff] [blame] | 94 | #if defined(TEGRA_PMX_PINS_HAVE_HSM) || defined(TEGRA_PMX_GRPS_HAVE_HSM) |
Stephen Warren | 899a5cb | 2015-02-24 14:08:26 -0700 | [diff] [blame] | 95 | /* Defines whether a pin group cfg's high-speed mode is enabled or not */ |
| 96 | enum pmux_hsm { |
| 97 | PMUX_HSM_DISABLE = 0, |
| 98 | PMUX_HSM_ENABLE = 1, |
| 99 | PMUX_HSM_NONE = -1, |
| 100 | }; |
| 101 | #endif |
| 102 | |
Stephen Warren | 9026dfd | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 103 | /* |
| 104 | * This defines the configuration for a pin, including the function assigned, |
| 105 | * pull up/down settings and tristate settings. Having set up one of these |
| 106 | * you can call pinmux_config_pingroup() to configure a pin in one step. Also |
| 107 | * available is pinmux_config_table() to configure a list of pins. |
| 108 | */ |
Stephen Warren | f4df605 | 2014-03-21 12:28:56 -0600 | [diff] [blame] | 109 | struct pmux_pingrp_config { |
Stephen Warren | 70b080f | 2014-03-21 15:58:03 -0600 | [diff] [blame] | 110 | u32 pingrp:16; /* pin group PMUX_PINGRP_... */ |
| 111 | u32 func:8; /* function to assign PMUX_FUNC_... */ |
| 112 | u32 pull:2; /* pull up/down/normal PMUX_PULL_...*/ |
| 113 | u32 tristate:2; /* tristate or normal PMUX_TRI_... */ |
Stephen Warren | 22d57fe | 2015-02-24 14:08:24 -0700 | [diff] [blame] | 114 | #ifdef TEGRA_PMX_PINS_HAVE_E_INPUT |
Stephen Warren | 70b080f | 2014-03-21 15:58:03 -0600 | [diff] [blame] | 115 | u32 io:2; /* input or output PMUX_PIN_... */ |
Stephen Warren | 22d57fe | 2015-02-24 14:08:24 -0700 | [diff] [blame] | 116 | #endif |
| 117 | #ifdef TEGRA_PMX_PINS_HAVE_LOCK |
Stephen Warren | 70b080f | 2014-03-21 15:58:03 -0600 | [diff] [blame] | 118 | u32 lock:2; /* lock enable/disable PMUX_PIN... */ |
Stephen Warren | 22d57fe | 2015-02-24 14:08:24 -0700 | [diff] [blame] | 119 | #endif |
| 120 | #ifdef TEGRA_PMX_PINS_HAVE_OD |
Stephen Warren | 70b080f | 2014-03-21 15:58:03 -0600 | [diff] [blame] | 121 | u32 od:2; /* open-drain or push-pull driver */ |
Stephen Warren | 22d57fe | 2015-02-24 14:08:24 -0700 | [diff] [blame] | 122 | #endif |
| 123 | #ifdef TEGRA_PMX_PINS_HAVE_IO_RESET |
Stephen Warren | 70b080f | 2014-03-21 15:58:03 -0600 | [diff] [blame] | 124 | u32 ioreset:2; /* input/output reset PMUX_PIN... */ |
Stephen Warren | 22d57fe | 2015-02-24 14:08:24 -0700 | [diff] [blame] | 125 | #endif |
| 126 | #ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL |
Stephen Warren | 70b080f | 2014-03-21 15:58:03 -0600 | [diff] [blame] | 127 | u32 rcv_sel:2; /* select between High and Normal */ |
| 128 | /* VIL/VIH receivers */ |
Stephen Warren | 9026dfd | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 129 | #endif |
Stephen Warren | d9f8def | 2015-02-24 14:08:30 -0700 | [diff] [blame^] | 130 | #ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV |
| 131 | u32 e_io_hv:2; /* select 3.3v tolerant receivers */ |
| 132 | #endif |
Stephen Warren | 97f9c68 | 2015-02-24 14:08:28 -0700 | [diff] [blame] | 133 | #ifdef TEGRA_PMX_PINS_HAVE_SCHMT |
| 134 | u32 schmt:2; /* schmitt enable */ |
| 135 | #endif |
| 136 | #ifdef TEGRA_PMX_PINS_HAVE_HSM |
| 137 | u32 hsm:2; /* high-speed mode enable */ |
| 138 | #endif |
Stephen Warren | 9026dfd | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 139 | }; |
| 140 | |
Stephen Warren | 22d57fe | 2015-02-24 14:08:24 -0700 | [diff] [blame] | 141 | #ifdef TEGRA_PMX_SOC_HAS_IO_CLAMPING |
Stephen Warren | db2937f | 2015-02-18 13:27:03 -0700 | [diff] [blame] | 142 | /* Set/clear the pinmux CLAMP_INPUTS_WHEN_TRISTATED bit */ |
Stephen Warren | f53f108 | 2014-04-22 14:37:54 -0600 | [diff] [blame] | 143 | void pinmux_set_tristate_input_clamping(void); |
Stephen Warren | db2937f | 2015-02-18 13:27:03 -0700 | [diff] [blame] | 144 | void pinmux_clear_tristate_input_clamping(void); |
Stephen Warren | f53f108 | 2014-04-22 14:37:54 -0600 | [diff] [blame] | 145 | #endif |
| 146 | |
Stephen Warren | 9026dfd | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 147 | /* Set the mux function for a pin group */ |
| 148 | void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func); |
| 149 | |
| 150 | /* Set the pull up/down feature for a pin group */ |
| 151 | void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd); |
| 152 | |
Stephen Warren | 9026dfd | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 153 | /* Set a pin group to tristate */ |
| 154 | void pinmux_tristate_enable(enum pmux_pingrp pin); |
| 155 | |
| 156 | /* Set a pin group to normal (non tristate) */ |
| 157 | void pinmux_tristate_disable(enum pmux_pingrp pin); |
| 158 | |
Stephen Warren | 22d57fe | 2015-02-24 14:08:24 -0700 | [diff] [blame] | 159 | #ifdef TEGRA_PMX_PINS_HAVE_E_INPUT |
Stephen Warren | 9026dfd | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 160 | /* Set a pin group as input or output */ |
| 161 | void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io); |
| 162 | #endif |
| 163 | |
Stephen Warren | 9026dfd | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 164 | /** |
| 165 | * Configure a list of pin groups |
| 166 | * |
| 167 | * @param config List of config items |
| 168 | * @param len Number of config items in list |
| 169 | */ |
Stephen Warren | f4df605 | 2014-03-21 12:28:56 -0600 | [diff] [blame] | 170 | void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config, |
| 171 | int len); |
Stephen Warren | 9026dfd | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 172 | |
Stephen Warren | 22d57fe | 2015-02-24 14:08:24 -0700 | [diff] [blame] | 173 | #ifdef TEGRA_PMX_SOC_HAS_DRVGRPS |
Stephen Warren | 9026dfd | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 174 | |
Stephen Warren | f4df605 | 2014-03-21 12:28:56 -0600 | [diff] [blame] | 175 | #define PMUX_SLWF_MIN 0 |
| 176 | #define PMUX_SLWF_MAX 3 |
| 177 | #define PMUX_SLWF_NONE -1 |
Stephen Warren | 9026dfd | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 178 | |
Stephen Warren | f4df605 | 2014-03-21 12:28:56 -0600 | [diff] [blame] | 179 | #define PMUX_SLWR_MIN 0 |
| 180 | #define PMUX_SLWR_MAX 3 |
| 181 | #define PMUX_SLWR_NONE -1 |
Stephen Warren | 9026dfd | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 182 | |
Stephen Warren | f4df605 | 2014-03-21 12:28:56 -0600 | [diff] [blame] | 183 | #define PMUX_DRVUP_MIN 0 |
| 184 | #define PMUX_DRVUP_MAX 127 |
| 185 | #define PMUX_DRVUP_NONE -1 |
Stephen Warren | 9026dfd | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 186 | |
Stephen Warren | f4df605 | 2014-03-21 12:28:56 -0600 | [diff] [blame] | 187 | #define PMUX_DRVDN_MIN 0 |
| 188 | #define PMUX_DRVDN_MAX 127 |
| 189 | #define PMUX_DRVDN_NONE -1 |
Stephen Warren | 9026dfd | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 190 | |
Stephen Warren | 9026dfd | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 191 | /* |
| 192 | * This defines the configuration for a pin group's pad control config |
| 193 | */ |
Stephen Warren | f4df605 | 2014-03-21 12:28:56 -0600 | [diff] [blame] | 194 | struct pmux_drvgrp_config { |
Stephen Warren | 70b080f | 2014-03-21 15:58:03 -0600 | [diff] [blame] | 195 | u32 drvgrp:16; /* pin group PMUX_DRVGRP_x */ |
| 196 | u32 slwf:3; /* falling edge slew */ |
| 197 | u32 slwr:3; /* rising edge slew */ |
| 198 | u32 drvup:8; /* pull-up drive strength */ |
| 199 | u32 drvdn:8; /* pull-down drive strength */ |
Stephen Warren | 3e9fb7b | 2015-02-24 14:08:25 -0700 | [diff] [blame] | 200 | #ifdef TEGRA_PMX_GRPS_HAVE_LPMD |
Stephen Warren | 70b080f | 2014-03-21 15:58:03 -0600 | [diff] [blame] | 201 | u32 lpmd:3; /* low-power mode selection */ |
Stephen Warren | 3e9fb7b | 2015-02-24 14:08:25 -0700 | [diff] [blame] | 202 | #endif |
| 203 | #ifdef TEGRA_PMX_GRPS_HAVE_SCHMT |
Stephen Warren | 70b080f | 2014-03-21 15:58:03 -0600 | [diff] [blame] | 204 | u32 schmt:2; /* schmidt enable */ |
Stephen Warren | 3e9fb7b | 2015-02-24 14:08:25 -0700 | [diff] [blame] | 205 | #endif |
| 206 | #ifdef TEGRA_PMX_GRPS_HAVE_HSM |
Stephen Warren | 70b080f | 2014-03-21 15:58:03 -0600 | [diff] [blame] | 207 | u32 hsm:2; /* high-speed mode enable */ |
Stephen Warren | 3e9fb7b | 2015-02-24 14:08:25 -0700 | [diff] [blame] | 208 | #endif |
Stephen Warren | 9026dfd | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 209 | }; |
| 210 | |
| 211 | /** |
| 212 | * Set the GP pad configs |
| 213 | * |
| 214 | * @param config List of config items |
| 215 | * @param len Number of config items in list |
| 216 | */ |
Stephen Warren | f4df605 | 2014-03-21 12:28:56 -0600 | [diff] [blame] | 217 | void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config, |
| 218 | int len); |
Stephen Warren | 9026dfd | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 219 | |
Stephen Warren | 22d57fe | 2015-02-24 14:08:24 -0700 | [diff] [blame] | 220 | #endif /* TEGRA_PMX_SOC_HAS_DRVGRPS */ |
Stephen Warren | 9026dfd | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 221 | |
Stephen Warren | f4df605 | 2014-03-21 12:28:56 -0600 | [diff] [blame] | 222 | struct pmux_pingrp_desc { |
Stephen Warren | 70b080f | 2014-03-21 15:58:03 -0600 | [diff] [blame] | 223 | u8 funcs[4]; |
Stephen Warren | 9026dfd | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 224 | #if defined(CONFIG_TEGRA20) |
Stephen Warren | 70b080f | 2014-03-21 15:58:03 -0600 | [diff] [blame] | 225 | u8 ctl_id; |
| 226 | u8 pull_id; |
Stephen Warren | 9026dfd | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 227 | #endif /* CONFIG_TEGRA20 */ |
| 228 | }; |
| 229 | |
Stephen Warren | f4df605 | 2014-03-21 12:28:56 -0600 | [diff] [blame] | 230 | extern const struct pmux_pingrp_desc *tegra_soc_pingroups; |
Stephen Warren | 9026dfd | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 231 | |
| 232 | #endif /* _TEGRA_PINMUX_H_ */ |