| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Anton Staaf | 71c2563 | 2011-10-17 16:46:10 -0700 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (c) 2011 The Chromium OS Authors. |
| Anton Staaf | 71c2563 | 2011-10-17 16:46:10 -0700 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef __MICROBLAZE_CACHE_H__ |
| 7 | #define __MICROBLAZE_CACHE_H__ |
| 8 | |
| 9 | /* |
| 10 | * The microblaze can have either a 4 or 16 byte cacheline depending on whether |
| 11 | * you are using OPB(4) or CacheLink(16). If the board config has not specified |
| 12 | * a cacheline size we assume the larger value of 16 bytes for DMA buffer |
| 13 | * alignment. |
| 14 | */ |
| 15 | #ifdef CONFIG_SYS_CACHELINE_SIZE |
| 16 | #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE |
| 17 | #else |
| 18 | #define ARCH_DMA_MINALIGN 16 |
| 19 | #endif |
| 20 | |
| 21 | #endif /* __MICROBLAZE_CACHE_H__ */ |